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1.发明申请METHOD OF FORMING AND PATTERNING CONFORMAL INSULATION LAYER IN VIAS AND ETCHED STRUCTURES 审中-公开在VIAS和蚀刻结构中形成和形成一致的绝缘层的方法
公开(公告)号：WO2011104550A2
公开(公告)日：2011-09-01
申请号：PCT/GB2011/050361
申请日：2011-02-24
Applicant: SPP PROCESS TECHNOLOGY SYSTEMS UK LIMITED , DITIZIO, Robert
Inventor： DITIZIO, Robert
IPC: H01L21/768 , B81B1/00
CPC classification number: H01L21/76898 , B81B2207/07 , B81C1/00087 , B81C2201/0112 , H01L21/02118 , H01L21/02271 , H01L21/02304 , H01L21/3065 , H01L21/30655
Abstract: Vias are formed in a substrate using an etch process that forms an undercut profile below the mask layer. The vias are coated with a conformal insulating layer and an etch process is applied to the structures to remove the insulating layer from horizontal surfaces while leaving the insulating layers on the vertical sidewalls of the vias. The top regions of the vias are protected during the etchback process by the undercut hardmask.
Abstract translation: 使用在掩模层下方形成底切轮廓的蚀刻工艺在衬底中形成通孔。 通孔用保形绝缘层涂覆，并且将蚀刻工艺施加到结构以从绝缘层移除绝缘层，同时将绝缘层留在通孔的垂直侧壁上。 通过底切硬掩模在回蚀过程中保护通孔的顶部区域。
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2.发明公开METHOD OF FORMING AND PATTERNING CONFORMAL INSULATION LAYER IN VIAS AND ETCHED STRUCTURES 审中-公开PROCESS FOR IN通道和蚀刻结构的制备和结构共形绝缘层的
公开(公告)号：EP2539930A2
公开(公告)日：2013-01-02
申请号：EP11713021.1
申请日：2011-02-24
Applicant: SPP Process Technology Systems UK Limited
Inventor： DITIZIO, Robert
IPC: H01L21/768 , B81B1/00
CPC classification number: H01L21/76898 , B81B2207/07 , B81C1/00087 , B81C2201/0112 , H01L21/02118 , H01L21/02271 , H01L21/02304 , H01L21/3065 , H01L21/30655
Abstract: Vias are formed in a substrate using an etch process that forms an undercut profile below the mask layer. The vias are coated with a conformal insulating layer and an etch process is applied to the structures to remove the insulating layer from horizontal surfaces while leaving the insulating layers on the vertical sidewalls of the vias. The top regions of the vias are protected during the etchback process by the undercut hardmask.
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