公开(公告)号：JPH1174372A

公开(公告)日：1999-03-16

申请号：JP18467098

申请日：1998-06-30

Applicant: ST MICROELECTRON INC

Inventor： SAGARWALA PERVEZ H ,  ZAMANIAN MEHDI ,  RAVI SANDARESAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide a CMOS integrated-circuit device which can be provided with an N-channel transistor and with a P-channel transistor, by a method wherein N type dopant impurities are implanted into a P-type silicon region, and the low-specific-resistance region of the N-channel transistor is formed. SOLUTION: An N type dopant is implanted, and the source-drain region of an N-channel transistor is formed. A photoresist mask 68 is placed on an N-type silicon active region 12. An N type dopant is implanted into a region which is not marked in a P-type silicon region 14, and a source-drain region 54 of the N-channel transistor is formed. A source-drain region 44' of a P- channel MOSFET 60 using only a first oxide layer is formed in a self-aligned manner, and a low-specific-resistance part 56 of the source-drain region 54 of an N-channel MOSFET 62 using a sidewall spacer 38 as a hole is formed in a self-adjusting manner. As a result, the complementary transistors 60, 62 whose characteristic is optimized are formed.