公开(公告)号：JPH11111872A

公开(公告)日：1999-04-23

申请号：JP21785498

申请日：1998-07-31

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSUI CHIU ,  SAGARWALA PERVEZ H ,  NGUYEN LOI

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To improve the insulation by providing an oxide layer having an increased thickness between the outer end of a polysilicon silicide layer and substrate disposed blow it. SOLUTION: A thin porous oxide is deposited at a comparatively low temp. to surround a polysilicon silicide layer 228, and this layer is anisotropically etched to form a pattern i.e., the lower corners 278 of a polysilicon layer 234 are rounded, compared with in prior art, to locate slightly apart from the top surface of an underlying n-type region 210 and the rounded corners are slightly laterally displaced from the boundary 276 of a side wall oxide spacer 230. These structures at the ends of a tunnel oxide layer 226 greatly improve the dielectric completeness at the lower corners of the polysilicon layer 228 by an oxidizing process for converting some of Si in the polysilicon layer 234 and a small amt. of the top surface of a substrate 206 into Si dioxide.

公开(公告)号：JPH1174372A

公开(公告)日：1999-03-16

申请号：JP18467098

申请日：1998-06-30

Applicant: ST MICROELECTRON INC

Inventor： SAGARWALA PERVEZ H ,  ZAMANIAN MEHDI ,  RAVI SANDARESAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide a CMOS integrated-circuit device which can be provided with an N-channel transistor and with a P-channel transistor, by a method wherein N type dopant impurities are implanted into a P-type silicon region, and the low-specific-resistance region of the N-channel transistor is formed. SOLUTION: An N type dopant is implanted, and the source-drain region of an N-channel transistor is formed. A photoresist mask 68 is placed on an N-type silicon active region 12. An N type dopant is implanted into a region which is not marked in a P-type silicon region 14, and a source-drain region 54 of the N-channel transistor is formed. A source-drain region 44' of a P- channel MOSFET 60 using only a first oxide layer is formed in a self-aligned manner, and a low-specific-resistance part 56 of the source-drain region 54 of an N-channel MOSFET 62 using a sidewall spacer 38 as a hole is formed in a self-adjusting manner. As a result, the complementary transistors 60, 62 whose characteristic is optimized are formed.

公开(公告)号：JPH11102229A

公开(公告)日：1999-04-13

申请号：JP15315798

申请日：1998-06-02

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSUI CHIU ,  SAGARWALA PERVEZ H

IPC: H01L21/8234 ,  G05F3/20 ,  G05F3/24 ,  G11C5/14 ,  H01L27/088 ,  H03F1/30

Abstract: PROBLEM TO BE SOLVED: To reduce the supply voltage and standby current of the integrated circuit by generating the absolute value of the effective threshold voltage of only a selected MOSFET less than the absolute value of an initial threshold voltage and inhibiting a high standby current at this time. SOLUTION: Only the well of one MOSFET selected between MOSFETs 12 and 13 of the integrated circuit 10 is selectively biased. The MOSFETs 12 and 13 have initial threshold voltages. Selective bias operation generates the absolute value of the effective threshold voltage of only the selected MOSFET which is less than the absolute value of the initial threshold voltage and the high standby current to the integrated circuit 10 is inhibited. Therefore, the MOSFETs 12 and 13 can be operated with supply voltages lower than about 1 V.