公开(公告)号：DE60124595T2

公开(公告)日：2007-09-13

申请号：DE60124595

申请日：2001-03-13

Applicant: ST MICROELECTRONICS ASIA

Inventor： OH WAH ,  ALDRIDGE CHRIS

IPC: H04B1/707 ,  H04B7/26

Abstract: Two preferred embodiments provide slot synchronization of an initial cell search. Two Finite Impulse Response (FIR) filters are used to correlate the synchronization codes transmitted in the downlink (forward link). A sign bit is taken after the first FIR to significantly reduce the hardware requirements for the second FIR, and thus the whole system. The correlated results from the second FIR can be further processed using two different algorithms. The first adds a square operation to the correlated results whilst the second takes the magnitude before passing to the next stage. Regardless of which algorithm is adopted, the results are accumulated (I and Q), instead of averaged, and stored in a memory location for each successive correlation over the same location in different slots. The physical-layer processor (PLP) then reads the accumulated results from the memory location and searches for the peak position corresponding to the slot boundary.

公开(公告)号：DE60124595D1

公开(公告)日：2006-12-28

申请号：DE60124595

申请日：2001-03-13

Applicant: ST MICROELECTRONICS ASIA

Inventor： OH WAH ,  ALDRIDGE CHRIS

IPC: H04B1/707 ,  H04B7/26

Abstract: Two preferred embodiments provide slot synchronization of an initial cell search. Two Finite Impulse Response (FIR) filters are used to correlate the synchronization codes transmitted in the downlink (forward link). A sign bit is taken after the first FIR to significantly reduce the hardware requirements for the second FIR, and thus the whole system. The correlated results from the second FIR can be further processed using two different algorithms. The first adds a square operation to the correlated results whilst the second takes the magnitude before passing to the next stage. Regardless of which algorithm is adopted, the results are accumulated (I and Q), instead of averaged, and stored in a memory location for each successive correlation over the same location in different slots. The physical-layer processor (PLP) then reads the accumulated results from the memory location and searches for the peak position corresponding to the slot boundary.

公开(公告)号：SG113440A1

公开(公告)日：2005-08-29

申请号：SG200206994

申请日：2002-11-19

Applicant: ST MICROELECTRONICS ASIA ,  AGENCY SCIENCE TECH & RES

Inventor： ALDRIDGE CHRIS ,  TAN WEE TIONG ,  SUN MINYING

IPC: H04L1/00 ,  H03M13/29 ,  H03M13/00

Abstract: A TFCI decoder (600) in accordance with the present invention comprises a comparator (605), which is coupled to receive encoded TFCI codewords (110) at a first input (610). At a second input (645), the comparator (605) is coupled to a TFCI candidate codeword generator (625) that generates all the possible candidate TFCI codewords (647) from all possible corresponding unencoded TFCI source data. When an encoded TFCI codeword (110) is received at the first input (610), the comparator (605) compares the TFCI codeword (110) with each of the possible candidate TFCI codewords (647) provided to the second input (645), and the corresponding TFCI source data (650) is identified. Subsequently, the identified TFCI source data (650) is latched in a TFCI source data memory (640) by a latch signal (620) provided from an output (630) of the comparator (605).