公开(公告)号：FR3005205A1

公开(公告)日：2014-10-31

申请号：FR1353841

申请日：2013-04-26

Applicant: ST MICROELECTRONICS GRENOBLE 2

Inventor： MANDIER CHRISTOPHE ,  MARCELLIN ALEXIS

IPC: H01L27/146 ,  H04N5/3745

Abstract: L'invention concerne un capteur d'image comprenant une matrice (AP21) de pixels (P'I,J) ayant chacun : un noeud d'accumulation (N0) couplé à un noeud capacitif de lecture (N1) par un transistor de transfert (TT) ; et un transistor de connexion (CT) couplant le noeud de lecture (N1) du pixel à un noeud intermédiaire (n2) du pixel, dans laquelle, chaque pixel a son noeud intermédiaire (n2) couplé à un noeud d'application d'un potentiel de réinitialisation (VS) par un transistor de réinitialisation (RT), et des pixels distincts ont leurs noeuds intermédiaires (n2) respectifs connectés ensemble par une piste conductrice de connexion (lct).

公开(公告)号：GB2516971A

公开(公告)日：2015-02-11

申请号：GB201314288

申请日：2013-08-09

Applicant: ST MICROELECTRONICS RES & DEV ,  ST MICROELECTRONICS GRENOBLE 2

Inventor： STORM GRAEME ,  MANDIER CHRISTOPHE

IPC: H01L27/146 ,  H04N5/30 ,  H04N5/335

Abstract: A pixel arrangement and method of use, comprising a photodiode 12, a reset transistor 18 controlled by a reset input voltage RST, a transfer gate transistor 14 controlled by a transfer gate voltage TG, configured to transfer charge from the photodiode to a charge transfer node (SN) 22 when in use and a source follower transistor 16 controlled by the node voltage and coupled to a source follower voltage when in use. During a read operation, at least one indentified voltage is increased, the identified voltage being a reset input voltage, source follower voltage, transfer gate voltage or transfer charge node voltage. Further a read transistor 20 may be included, controlled during reading by a read voltage set to a read value, which may have a time period exceeding the period during which the identified voltage is increased. Preferably, during the read operation, the transfer gate voltage signal is changed from a lower first voltage level to an intermediate voltage level and then from the intermediate voltage to a second higher voltage. The reverse may also occur, for example, second, intermediate first voltage sequence. The reset signal may be pulsed at the beginning of the read operation and at the same time as the read voltage is set to the read value. A capacitor 32 coupled to the charge transfer node may be configured to increase the voltage on the node during a read.