公开(公告)号：GB2499374A

公开(公告)日：2013-08-21

申请号：GB201201530

申请日：2012-01-30

Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS RES & DEV

Inventor： FERRIS ANDREW ,  URZI IGNAZIO-ANTONINO

IPC: G06F1/08

Abstract: Disclosed is a circuit arrangement with two clock sources and circuitry configured to supply a clock signal to an associated circuit. The circuitry is configured to change the clock signal from one frequency to another frequency such that no clock signal is supplied when changing the frequencies. The first source may be an oscillator, and the second may be a phase lock loop, which may setup to attain lock when the clock signal from the first clock source is being supplied. The circuit arrangement may have delay locked loop circuitry to provide a controllable delay. The associated circuit may have a plurality of taps, such that the selection of the taps determines the period for which the clock is not supplied and/or the time taken to change the supplied clock frequency. The circuit arrangement may be consist of a pair of dies, the first die having a processor and the second having a memory that stores boot data for the processor.

公开(公告)号：GB2497314A

公开(公告)日：2013-06-12

申请号：GB201120959

申请日：2011-12-06

Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS RES & DEV ,  ST MICROELECTRONICS SA

Inventor： FERRIS ANDREW ,  URZI IGNAZIO ANTONINO ,  TEISSIER PASCAL

IPC: G06F13/40

Abstract: An integrated circuit has two blocks, which may be transmitters or may be receivers. The first transmits n bits and the second transmits m bits. The blocks can be configured to operate on two independent busses or can be configured to operate on a single n+m bit bus. The blocks may have the same circuitry, connected by a communication channel. The blocks may be arranged symmetrically about the channel. When operating on a single bus, one block may be a master and the other a slave. In this mode, a clock signal may be supplied by only one of the two blocks. One of the blocks may be put into a low power mode while the second block operates independently. The circuit may be used in video processing, the combined bus being used for three dimensional images and the separate busses being used for two dimensional images.