公开(公告)号：JP2001168917A

公开(公告)日：2001-06-22

申请号：JP2000301580

申请日：2000-10-02

Applicant: ST MICROELECTRONICS INC

Inventor： ANDREW JONES ,  JOHN A CARY ,  RAMANADIN BERNARD ,  HASEGAWA ATSUSHI

IPC: G06F13/362 ,  G06F13/364 ,  G06F13/40 ,  G06F15/78 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit that is provided with a packet router, whose extension is facilitated. SOLUTION: This invention provides the integrated circuit that is provided with a packet router where function modules are connected by respective ports. One of the ports acts like a socket port with respect to an extension socket. The extension socket provides a plurality of additional extension ports, to which additional function modules can be connected. All of the ports, including the extension socket port and connected to the packet router, preferably exist in a common address space of the integrated circuit.

公开(公告)号：JP2001147858A

公开(公告)日：2001-05-29

申请号：JP2000301559

申请日：2000-10-02

Applicant: ST MICROELECTRONICS INC

Inventor： D SHIMIZU ,  ANDREW JONES

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To efficiently perform access to a common in a cache memory system. SOLUTION: A computer system is provided with a memory system, and at least one part of the memory systems is designated as a common memory. A bus mechanism connected with the memory system with a transaction as a base is provided with a cache coherency transaction defined in the transaction set. A processor having a cache memory is connected through the bus mechanism with the transaction as a base with the memory system. A system component connected with the bus mechanism is provided with a logic for specifying a cache coherence policy. Then, the cache transaction is started according to the cache policy on the bus mechanism specified by the logic in the system component. The logic in the processor responds to the cache transaction started by executing the cache operation specified by the cache transaction.