公开(公告)号：JP2001168917A

公开(公告)日：2001-06-22

申请号：JP2000301580

申请日：2000-10-02

Applicant: ST MICROELECTRONICS INC

Inventor： ANDREW JONES ,  JOHN A CARY ,  RAMANADIN BERNARD ,  HASEGAWA ATSUSHI

IPC: G06F13/362 ,  G06F13/364 ,  G06F13/40 ,  G06F15/78 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit that is provided with a packet router, whose extension is facilitated. SOLUTION: This invention provides the integrated circuit that is provided with a packet router where function modules are connected by respective ports. One of the ports acts like a socket port with respect to an extension socket. The extension socket provides a plurality of additional extension ports, to which additional function modules can be connected. All of the ports, including the extension socket port and connected to the packet router, preferably exist in a common address space of the integrated circuit.

公开(公告)号：DE60025114D1

公开(公告)日：2006-02-02

申请号：DE60025114

申请日：2000-09-25

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN ,  WRIGHT STEPHEN JAMES ,  RAMANADIN BERNARD

IPC: G01R31/319 ,  G06F11/00 ,  G06F11/26

公开(公告)号：DE60028319D1

公开(公告)日：2006-07-06

申请号：DE60028319

申请日：2000-09-25

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN ,  WRIGHT STEPHEN JAMES ,  RAMANADIN BERNARD

IPC: G06F11/36 ,  G06F13/22

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.