公开(公告)号：JP2001147831A

公开(公告)日：2001-05-29

申请号：JP2000299928

申请日：2000-09-29

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN ,  GEARTY MARGARET ROSE ,  FARRALL GLENN A ,  HASEGAWA ATSUSHI ,  RICH ANTHONY WILLIS

IPC: G06F11/28 ,  G06F11/22 ,  G06F11/26 ,  G06F11/36 ,  G06F15/78

Abstract: PROBLEM TO BE SOLVED: To provide an improved interface for transferring debug information. SOLUTION: A microcomputer having a processor and a debug circuit is provided with an exclusive link for transferring information between the processor and the debug circuit for supporting a debug operation. The processor supplies program counter information, and the program counter information is stored in the memory map type register of the debug circuit. The program counter information may be obtained as the value of a processor program counter positioned at the write back stage of a processor pipe line. Also, trace information including message information is transferred through the exclusive link in a non-intrusive mode. This microcomputer may be constituted as a single integrated circuit.

公开(公告)号：DE60039481D1

公开(公告)日：2008-08-28

申请号：DE60039481

申请日：2000-09-25

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN ,  GEARTY MARGARET ROSE ,  FARRALL GLENN A ,  HASEGAWA ATSUSHI ,  RICH ANTHONY WILLIS

IPC: G06F11/28 ,  G06F11/36 ,  G06F11/22 ,  G06F11/26 ,  G06F15/78

Abstract: A microcomputer includes a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. The processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link.