公开(公告)号：JP2001154876A

公开(公告)日：2001-06-08

申请号：JP2000301930

申请日：2000-10-02

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN

IPC: G06F11/28 ,  G06F11/36 ,  G06F15/78

Abstract: PROBLEM TO BE SOLVED: To provide an improved method and device for executing a debug operation on a microcomputer. SOLUTION: This computer system is provided with a central processing unit and a memory unit connected with the central processing unit, and one set of watch points are defined in the computer system. Each watch point in the set of watch points is provided with a programmable precondition register which stores a set of precondition codes which are made the same for each watch point in the set of watch points. Moreover, each watch point is provided with a programmable action register for storing a set of action codes which are made the same for each watch point in the set of watch points. Moreover, this computer system is provided with a set of latches which are respectively equipped with inputs and outputs.

公开(公告)号：JP2001147836A

公开(公告)日：2001-05-29

申请号：JP2000301822

申请日：2000-10-02

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN ,  RICH ANTHONY W

IPC: G06F11/28 ,  G06F11/36 ,  G06F15/78

Abstract: PROBLEM TO BE SOLVED: To provide an improved method and device for operating a debugging operation on a microcomputer. SOLUTION: This computer system is provided with at least one central processing unit and a memory unit connected with at least one central processor, and a set of watch points are decided on the computer system. Each watch point of the set of watch points is provided with a programmable preconditioned register and a programmable action register. Moreover, this computer system is provided with one set of latches and a selecting circuit for selecting one latch of the set of latches for connecting the output of the action register with the input of the selected latch.

公开(公告)号：JP2001154875A

公开(公告)日：2001-06-08

申请号：JP2000301698

申请日：2000-10-02

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN

IPC: G06F11/28 ,  G06F11/36 ,  G06F15/78

Abstract: PROBLEM TO BE SOLVED: To provide an improved device and method for executing a debugging operation on a microcomputer. SOLUTION: This computer system is provided with one set of watch points fixed in a computer. Each watch point in the set of watch points is provided with a programmable precondition register for storing a set of pre-condition codes, and the set of precondition codes are made the same to each watch point in the set of watch points. Moreover, this computer system is provided with a comparator of which input is connected with the precondition register, and the comparator compares at least one precondition code in the set of precondition codes with a data value in the computer system, and supplies a signal to the action register in response to this.

公开(公告)号：JP2001147831A

公开(公告)日：2001-05-29

申请号：JP2000299928

申请日：2000-09-29

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN ,  GEARTY MARGARET ROSE ,  FARRALL GLENN A ,  HASEGAWA ATSUSHI ,  RICH ANTHONY WILLIS

IPC: G06F11/28 ,  G06F11/22 ,  G06F11/26 ,  G06F11/36 ,  G06F15/78

Abstract: PROBLEM TO BE SOLVED: To provide an improved interface for transferring debug information. SOLUTION: A microcomputer having a processor and a debug circuit is provided with an exclusive link for transferring information between the processor and the debug circuit for supporting a debug operation. The processor supplies program counter information, and the program counter information is stored in the memory map type register of the debug circuit. The program counter information may be obtained as the value of a processor program counter positioned at the write back stage of a processor pipe line. Also, trace information including message information is transferred through the exclusive link in a non-intrusive mode. This microcomputer may be constituted as a single integrated circuit.

公开(公告)号：DE60036059D1

公开(公告)日：2007-10-04

申请号：DE60036059

申请日：2000-09-25

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN

IPC: G06F11/28 ,  G06F11/36 ,  G06F15/78

Abstract: A computer system, including a central processing unit and a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints including a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints, a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints, a set of latches, each latch having an input and an output, and circuitry that couples at least one latch in the set of latches to at least two watchpoints in the set of watchpoints so that there is a predetermined relationship between triggering of the at least two watchpoints. A method of filtering debugging data in a computer system is also provided.

公开(公告)号：DE60028319D1

公开(公告)日：2006-07-06

申请号：DE60028319

申请日：2000-09-25

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN ,  WRIGHT STEPHEN JAMES ,  RAMANADIN BERNARD

IPC: G06F11/36 ,  G06F13/22

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

公开(公告)号：DE60044767D1

公开(公告)日：2010-09-16

申请号：DE60044767

申请日：2000-09-25

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN

IPC: G06F11/28 ,  G06F11/36 ,  G01R31/3185 ,  G06F11/26 ,  G06F15/78

公开(公告)号：DE60039481D1

公开(公告)日：2008-08-28

申请号：DE60039481

申请日：2000-09-25

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN ,  GEARTY MARGARET ROSE ,  FARRALL GLENN A ,  HASEGAWA ATSUSHI ,  RICH ANTHONY WILLIS

IPC: G06F11/28 ,  G06F11/36 ,  G06F11/22 ,  G06F11/26 ,  G06F15/78

Abstract: A microcomputer includes a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. The processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link.

公开(公告)号：DE60025114D1

公开(公告)日：2006-02-02

申请号：DE60025114

申请日：2000-09-25

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN ,  WRIGHT STEPHEN JAMES ,  RAMANADIN BERNARD

IPC: G01R31/319 ,  G06F11/00 ,  G06F11/26

公开(公告)号：DE60024554D1

公开(公告)日：2006-01-12

申请号：DE60024554

申请日：2000-09-25

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN ,  RICH ANTHONY WILLIS

IPC: G01R31/319 ,  G06F11/00 ,  G06F11/26 ,  G06F11/36 ,  G06F13/42

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.