公开(公告)号：DE69919114D1

公开(公告)日：2004-09-09

申请号：DE69919114

申请日：1999-09-28

Applicant: ST MICROELECTRONICS INC

Inventor： KASPER CHRISTIAN D ,  GURITZ ELMER H

IPC: H04L12/56 ,  H04L13/08 ,  H04L29/06 ,  G06F13/28

Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion, such as in the receive port of an HDLC controller is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

公开(公告)号：DE69919114T2

公开(公告)日：2005-07-28

申请号：DE69919114

申请日：1999-09-28

Applicant: ST MICROELECTRONICS INC

Inventor： KASPER CHRISTIAN D ,  GURITZ ELMER H

IPC: H04L12/56 ,  H04L13/08 ,  H04L29/06 ,  G06F13/28

Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion, such as in the receive port of an HDLC controller is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

公开(公告)号：DE69132387T2

公开(公告)日：2001-02-01

申请号：DE69132387

申请日：1991-05-23

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU C ,  HAN YU-PIN ,  GURITZ ELMER H

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

公开(公告)号：DE69132387D1

公开(公告)日：2000-10-05

申请号：DE69132387

申请日：1991-05-23

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU C ,  HAN YU-PIN ,  GURITZ ELMER H

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.