公开(公告)号：DE69534542D1

公开(公告)日：2005-12-01

申请号：DE69534542

申请日：1995-07-11

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU C ,  HUANG KUEI-WU

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/60

Abstract: A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack. The stack is then etched to form an opening in the insulation layer exposing the thin dielectric layer which acts as an etch stop during the stack etch process. The thin dielectric layer is then etched in the opening to expose the first conductive layer. A conductor is then formed in the opening contacting the underlying conductive structure. The thin dielectric under the insulation layer and on the sides of the opening near the conductive structure will increase the distance and help to electrically isolate the conductor at the edge of the contact opening from nearby active areas and devices.

公开(公告)号：DE69526486T2

公开(公告)日：2002-10-10

申请号：DE69526486

申请日：1995-11-30

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU C ,  BRYANT FRANK R ,  NGUYEN LOI N

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8239 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L21/60 ,  H01L21/3105

公开(公告)号：DE69526486D1

公开(公告)日：2002-05-29

申请号：DE69526486

申请日：1995-11-30

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU C ,  BRYANT FRANK R ,  NGUYEN LOI N

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8239 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L21/60 ,  H01L21/3105

公开(公告)号：DE69133300T2

公开(公告)日：2004-04-22

申请号：DE69133300

申请日：1991-05-23

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU C ,  HAN YU-PIN ,  GURITZ ELMER

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

公开(公告)号：DE69133300D1

公开(公告)日：2003-09-04

申请号：DE69133300

申请日：1991-05-23

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU C ,  HAN YU-PIN ,  GURITZ ELMER

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

公开(公告)号：DE69132387T2

公开(公告)日：2001-02-01

申请号：DE69132387

申请日：1991-05-23

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU C ,  HAN YU-PIN ,  GURITZ ELMER H

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

公开(公告)号：DE69132387D1

公开(公告)日：2000-10-05

申请号：DE69132387

申请日：1991-05-23

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU C ,  HAN YU-PIN ,  GURITZ ELMER H

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.