公开(公告)号：JP2001250383A

公开(公告)日：2001-09-14

申请号：JP2001063625

申请日：2001-03-07

Applicant: ST MICROELECTRONICS INC

Inventor： LAURENT DUANE GILES ,  GURITZ ELMER HENRY ,  WORLEY JAMES LEON

IPC: G11C11/407 ,  G11C11/408

Abstract: PROBLEM TO BE SOLVED: To provide a technology for controlling a booststrap circuit for boosting a voltage level generated on a word line of a DRAM. SOLUTION: The booststrap circuit is enabled in a period succeeding to initial power-up of a sense amplifier of a memory device during a performing period of memory access operation, the time when voltage generated on a selected bit line intersects the prescribed voltage level is detected, after that, the bootstrap circuit is enabled. Thus, the prescribed period elapse between turning-on of the sense amplifier and activation of the bootstrap circuit, therefore, influence affected to operation of the bootstrap circuit by a noise introduced by turning on the sense amplifier is reduced.

公开(公告)号：JP2000243081A

公开(公告)日：2000-09-08

申请号：JP2000043897

申请日：2000-02-22

Applicant: ST MICROELECTRONICS INC

Inventor： GURITZ ELMER HENRY

IPC: G11C11/407 ,  G05F1/46 ,  G05F3/24 ,  G11C7/14 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4099 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide reference voltage having high immunity for a noise by providing a voltage divider which is connected to a voltage supply source, decides reference voltage, and supplies a voltage output signal under control of a feedback control signal, and a feedback buffer amplifier for supplying a feedback control signal to a voltage divider. SOLUTION: A feedback buffer amplifier is provided in a reference voltage generator, and a N-type transistor M0 and a P-type transistor M1 which are connected in series between VDD and ground are provided. Gates of the transistors M0. M1 are connected respectively to a N-drive output signal 36 and a P-drive output signal 38, also, the transistors M0 and M1 are connected by a node D, the node D is connected to a substrate of the transistor M1, and supplies a feedback control signal 34 to a delay element. In order to secure quick response, the transistors M0, M1 has small size, and the node D is subjected to light load.

公开(公告)号：DE69330335D1

公开(公告)日：2001-07-19

申请号：DE69330335

申请日：1993-11-29

Applicant: ST MICROELECTRONICS INC

Inventor： GURITZ ELMER HENRY ,  CHAN TSIU CHIU

IPC: G11C17/12 ,  H01L27/112 ,  G11C7/00

Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.

公开(公告)号：DE60027339D1

公开(公告)日：2006-05-24

申请号：DE60027339

申请日：2000-02-17

Applicant: ST MICROELECTRONICS INC

Inventor： GURITZ ELMER HENRY

IPC: G11C11/407 ,  G11C11/409 ,  G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C7/14 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4099 ,  H01L21/822 ,  H01L27/04

Abstract: A reference voltage generator includes a voltage divider connected to a voltage supply and a feedback buffer amplifier. The divider supplies at least one voltage output signal to the feedback buffer amplifier under control of a feedback control signal supplied by the feedback buffer amplifier. The reference voltage generator may include a delay element coupled between the voltage divider and the feedback buffer amplifier in-line with the feedback control signal and a low impedance output buffer that receives the voltage output signal from the voltage divider and supplies the reference voltage at an output node. The reference voltage may be supplied to the reference plates of bit storage capacitors within the memory cells. The storage capacitors can be protected by including a clamping circuit that maintains the output node at a voltage between the voltages of the two voltage supply terminals.

公开(公告)号：DE60137556D1

公开(公告)日：2009-03-19

申请号：DE60137556

申请日：2001-02-22

Applicant: ST MICROELECTRONICS INC

Inventor： LAURENT DUANE GILES ,  GURITZ ELMER HENRY ,  WORLEY JAMES LEON

IPC: G11C11/407 ,  G11C11/408

Abstract: A dynamic random access memory device has bootstrap circuitry that boosts a voltage level appearing on word lines. During execution of a memory access operation, the bootstrap circuitry is enabled a period of time following the power up of sense amplifiers. A circuit senses when the voltage appearing on a select bit line crosses a predetermined voltage level, and enables the bootstrap circuitry thereafter. A period of time elapses between the sense amplifiers turning on and the activation of the bootstrap circuitry, thereby reducing noise introduced from the sense amplifiers turning on from impacting the operation of the bootstrap circuitry.

公开(公告)号：DE69330335T2

公开(公告)日：2002-05-29

申请号：DE69330335

申请日：1993-11-29

Applicant: ST MICROELECTRONICS INC

Inventor： GURITZ ELMER HENRY ,  CHAN TSIU CHIU

IPC: G11C17/12 ,  H01L27/112 ,  G11C7/00

Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.