公开(公告)号：JP2000174017A

公开(公告)日：2000-06-23

申请号：JP21682199

申请日：1999-07-30

Applicant: ST MICROELECTRONICS INC

Inventor： BRADY JAMES ,  LAURENT DUANE GILES

IPC: H01L21/3205 ,  H01L23/52 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To reduce the propagation delay time of an electric signal transmitted along a conductor in a circuit by extending a second substantially parallel electrically coupled conductor near and along a first electric signal carrying conductor extending from a first section of the circuit to a second section. SOLUTION: A conductor 120 extending from a first circuit 112 located in a first section 114 of an integrated circuit to a second circuit 116 located in a second section 118 is pref. 1000 μm long or more, the conductor 120 has a first conductor 120a and a second and third conductors 120b, 120c, each extending parallel to and along the first conductor 120a. The second conductor 120b is made of a conductive metal or material, pref. a low resistance material contg. Cu, W, Al, polysilicon or other substance, etc. This increases the velocity of an-electric signal propagating along the conductor 120.

公开(公告)号：JP2001250383A

公开(公告)日：2001-09-14

申请号：JP2001063625

申请日：2001-03-07

Applicant: ST MICROELECTRONICS INC

Inventor： LAURENT DUANE GILES ,  GURITZ ELMER HENRY ,  WORLEY JAMES LEON

IPC: G11C11/407 ,  G11C11/408

Abstract: PROBLEM TO BE SOLVED: To provide a technology for controlling a booststrap circuit for boosting a voltage level generated on a word line of a DRAM. SOLUTION: The booststrap circuit is enabled in a period succeeding to initial power-up of a sense amplifier of a memory device during a performing period of memory access operation, the time when voltage generated on a selected bit line intersects the prescribed voltage level is detected, after that, the bootstrap circuit is enabled. Thus, the prescribed period elapse between turning-on of the sense amplifier and activation of the bootstrap circuit, therefore, influence affected to operation of the bootstrap circuit by a noise introduced by turning on the sense amplifier is reduced.

公开(公告)号：JP2002260399A

公开(公告)日：2002-09-13

申请号：JP2001395615

申请日：2001-12-27

Applicant: ST MICROELECTRONICS INC

Inventor： LAURENT DUANE GILES

IPC: G01R31/28 ,  G01R31/319 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a memory device which can decide sensitivity of a sense amplifier. SOLUTION: This dynamic random access memory(DRAM) has a pair of bit lines provided with first bit lines and second bit lines. Memory cells and sense amplifiers are coupled to the bit lines. First characterization cells are coupled between the first bit lines and a first reference supply line. The first characterization cell has a capacitor. In the same way, Second characterization cells are coupled between the first bit lines and a first reference supply line. The second characterization cell also has a capacitor, but preferably, has a different capacitor. In an appropriate embodiment, a same characterization cell is coupled to the second bit lines.

公开(公告)号：DE60322772D1

公开(公告)日：2008-09-25

申请号：DE60322772

申请日：2003-04-16

Applicant: ST MICROELECTRONICS INC

Inventor： LAURENT DUANE GILES

IPC: G11C5/14 ,  H03K19/00 ,  G11C11/407

Abstract: A circuit is disclosed for monitoring a reference voltage generated in a semiconductor memory device to facilitate a memory access operation. The circuit utilizes a pair of Schmitt trigger circuits. A first of the Schmitt trigger circuits detects the voltage appearing on the output of a reference voltage generator falling below a minimum threshold voltage level. A second of the Schmitt trigger circuits detects the output voltage of the reference voltage generator exceeding a maximum threshold voltage level. The circuit may further include reset circuitry for initially placing predetermined voltage levels on the inputs of the Schmitt trigger circuits. An output circuit receives the output of each Schmitt trigger circuit and generates an output signal having a value indicative of whether the output of the reference voltage generator is not within an acceptable voltage range.

公开(公告)号：DE60137556D1

公开(公告)日：2009-03-19

申请号：DE60137556

申请日：2001-02-22

Applicant: ST MICROELECTRONICS INC

Inventor： LAURENT DUANE GILES ,  GURITZ ELMER HENRY ,  WORLEY JAMES LEON

IPC: G11C11/407 ,  G11C11/408

Abstract: A dynamic random access memory device has bootstrap circuitry that boosts a voltage level appearing on word lines. During execution of a memory access operation, the bootstrap circuitry is enabled a period of time following the power up of sense amplifiers. A circuit senses when the voltage appearing on a select bit line crosses a predetermined voltage level, and enables the bootstrap circuitry thereafter. A period of time elapses between the sense amplifiers turning on and the activation of the bootstrap circuitry, thereby reducing noise introduced from the sense amplifiers turning on from impacting the operation of the bootstrap circuitry.

公开(公告)号：DE60214072D1

公开(公告)日：2006-10-05

申请号：DE60214072

申请日：2002-04-22

Applicant: ST MICROELECTRONICS INC

Inventor： LAURENT DUANE GILES

IPC: G06F11/10 ,  G06F12/16 ,  G11C29/00

Abstract: A circuit and method are disclosed for reducing soft errors in dynamic memory devices using error checking and correcting. In an exemplary embodiment, a memory device includes a dual port memory having a first port for externally-initiated memory access operations and a second port for handling memory access operations associated with error checking and error correction operations. An error module, coupled to the second port of the dual port memory, performs an error checking operation on words read from the dual port memory. An error controller, coupled to the error module, controls the error module to perform error check operations on each word sequentially read from the dual port memory through the second port thereof. The error checking is performed substantially in parallel with externally-initiated memory access operations performed using the first port of the dual port memory. The error module may also generate a corrected word for a word that is detected by the error module as having a correctable error. The error controller may replace in the dual port memory the word having the correctable error with the corrected word.