公开(公告)号：JP2003114795A

公开(公告)日：2003-04-18

申请号：JP2002261802

申请日：2002-09-06

Applicant: ST MICROELECTRONICS INC

Inventor： HOSSAIN RAZAK ,  HUANG LUN-BIN

IPC: G06F9/38 ,  G06F7/00 ,  G06F7/02 ,  G06F7/50 ,  G06F7/505 ,  G06F9/32

Abstract: PROBLEM TO BE SOLVED: To provide technique for improving processing speed of comparison following addition in a computation system. SOLUTION: This computation system comprises plural full adders, and each of them receives reversal for each bit of single bits in third data, single bits in second data, and single bits in first data, and supplies a total output and a carry output. An exclusive OR logic module receives the total output of the first one of the full adders and the carry output of the second one of the full adders, and supplies an exclusive OR output. An AND logic module has plural inputs and an AND output. The exclusive OR output is electrically connected to one of the plural inputs of the AND logic module. The AND output supplies a signal representing if the first data are equal to the total of the second data and the third data.