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公开(公告)号：JP2003114795A
公开(公告)日：2003-04-18
申请号：JP2002261802
申请日：2002-09-06
Applicant: ST MICROELECTRONICS INC
Inventor： HOSSAIN RAZAK , HUANG LUN-BIN
Abstract: PROBLEM TO BE SOLVED: To provide technique for improving processing speed of comparison following addition in a computation system. SOLUTION: This computation system comprises plural full adders, and each of them receives reversal for each bit of single bits in third data, single bits in second data, and single bits in first data, and supplies a total output and a carry output. An exclusive OR logic module receives the total output of the first one of the full adders and the carry output of the second one of the full adders, and supplies an exclusive OR output. An AND logic module has plural inputs and an AND output. The exclusive OR output is electrically connected to one of the plural inputs of the AND logic module. The AND output supplies a signal representing if the first data are equal to the total of the second data and the third data.
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公开(公告)号：DE602004010480D1
公开(公告)日：2008-01-17
申请号：DE602004010480
申请日：2004-12-17
Applicant: ST MICROELECTRONICS INC
Inventor： RAJGOPAL SURESH , HUANG LUN-BIN , RICHARDSON NICHOLAS JULIAN
Abstract: Internet Protocol address prefixes (4-32) are hashed into hash tables (T4-T32) allocated memory blocks on demand after collisions occur for both a first hash and a single rehash. The number of memory blocks allocated to each hash table (T4-T32) is limited, with additional prefixes handled by an overflow content addressable memory (103). Each hash table (T4-T32) contains only prefixes of a particular length, with different hash tables (T4-T32) containing prefixes of different lengths. Only a subset of possible prefix lengths are accommodated by the hash tables (T4-T32), with a remainder of prefixes handled by the content addressable memory (103) or a similar alternate address lookup facility.
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