公开(公告)号：DE602004000890D1

公开(公告)日：2006-06-22

申请号：DE602004000890

申请日：2004-04-30

Applicant: ST MICROELECTRONICS INC

Inventor： FRUHAUF SERGE ,  LEAMING TAYLOR J ,  POMET ALAIN C

IPC: G06K19/07 ,  G06K7/00

Abstract: An integrated circuit for a smart card may include a universal serial bus (USB) transceiver for communicating with a USB host device, and a microprocessor connected to the USB transceiver and operable in a test mode and a user mode. When in the test mode, the microprocessor may perform a test operation based upon receiving at least one test vendor specific request (VSR) from the USB host device via the at least one USB transceiver. By way of example, the test operation may include scan testing the microprocessor's control logic, detecting a status of at least one buffer and communicating the status to the USB host device, writing test data to at least one designated buffer and sending the test data from the at least one designated buffer to the USB host device, and/or operating with reduced power.

公开(公告)号：AU7787401A

公开(公告)日：2002-01-30

申请号：AU7787401

申请日：2001-07-13

Applicant: SCHLUMBERGER MALCO INC ,  ST MICROELECTRONICS INC

Inventor： LEYDIER ROBERT A ,  POMET ALAIN C

IPC: G06F1/04 ,  G06K7/00 ,  G06K19/07 ,  H04L7/033 ,  H04L7/04 ,  H04L7/10 ,  G06F1/12

公开(公告)号：EP1311936A4

公开(公告)日：2009-01-21

申请号：EP01955819

申请日：2001-07-13

Applicant: SCHLUMBERGER MALCO INC ,  ST MICROELECTRONICS INC

Inventor： LEYDIER ROBERT A ,  POMET ALAIN C

IPC: G06F1/04 ,  G06K7/00 ,  G06K19/07 ,  H04L7/033 ,  H04L7/04 ,  H04L7/10 ,  G06F1/12

CPC classification number: G06K19/07733 ,  G06F1/04 ,  G06K7/0008 ,  G06K19/07 ,  H04L7/0331 ,  H04L7/0337 ,  H04L7/04 ,  H04L7/10

Abstract: A method and device is disclosed for generating a local clock signal CLK1X (172) from Universal Synchronous Bus downstream-received differential signals DM and DP carrying the downstream received bit-serial signal. The method and device does not require the use of a crystal or resonator. Counters (312, 310, 305, 301) are used to determine a number of periods of a free-running high frequency clock signal (164) contained within in a known number of bit periods of the downstream received bit-serial signal (146). The counter values are divided by the known number of bit periods of the received bit-serial signal (146) to determine a bit period of the received bit-serial signal (146). The local clock signal (172) may be phase-locked with the received bit serial signal (146). The local clock period is updated on an ongoing manner by downstream known received traffic.