公开(公告)号：JP2002033294A

公开(公告)日：2002-01-31

申请号：JP2001179122

申请日：2001-06-13

Applicant: ST MICROELECTRONICS INC

Inventor： WANG FUCHAO ,  HWANG MING

IPC: H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit, having a silicide where sheet resistance is low and probability of peeling of a film or oxidation of metal is reduced, and to provide its manufacturing method. SOLUTION: The silicide, having variable inner metal concentration which is adjusted to the surface condition in an interface between the silicide and an adjacent layer, is used in an integrated circuit. Higher ratio (silicon rich) of silicon/metal is used in an interface with an adjacent layer, lattice nonconformity in the interface is reduced, and probability of peeling of a film is reduced. A lower ratio of silicon/metal is used in the central region of the silicide, and the specific resistance is reduced.

公开(公告)号：DE60121258D1

公开(公告)日：2006-08-17

申请号：DE60121258

申请日：2001-05-18

Applicant: ST MICROELECTRONICS INC

Inventor： WANG FUCHAO ,  FANG MING

IPC: H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

Abstract: A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.