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    Cache memory which evicts data which has been accessed in preference to data which has not been accessed
    2.
    发明专利
    Cache memory which evicts data which has been accessed in preference to data which has not been accessed 未知

    公开(公告)号：GB2454810A

    公开(公告)日：2009-05-20

    申请号：GB0821080

    申请日：2008-11-18

    Applicant: ST MICROELECTRONICS LTD

    Inventor： JONES ANDREW MICHAEL ,  RYAN STUART

    IPC: G06F12/12 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/126

    Abstract: A cache memory 1, for providing rapid access to data from a system memory 105, can identify whether a region has been accessed by an external device, such as a processor 101 or DMA controller 107. When data is loaded into the cache, it is loaded into a region which has been accessed in preference to one which has not. If there are no free regions and no regions that have been accessed, the data may fail to load data into the cache. The loading of data may be a pre-fetch operation. The cache may have a status value for each line in the cache which indicates whether the line has been accessed. The status value may be stored with the address tag. The cache memory may be a level 2 cache.

    Cache memory which pre-fetches data when an address register is written
    4.
    发明专利
    Cache memory which pre-fetches data when an address register is written 未知

    公开(公告)号：GB2454811A

    公开(公告)日：2009-05-20

    申请号：GB0821081

    申请日：2008-11-18

    Applicant: ST MICROELECTRONICS LTD

    Inventor： JONES ANDREW MICHAEL ,  RYAN STUART

    IPC: G06F12/08 ,  G06F12/0862

    Abstract: A cache memory 1 has a register 23 in which a value may be stored. When a value is written to that register, data is pre-fetched into the cache from an address in the system memory defined by the value that was written. The amount of data pre-fetched may also be defined by the value written. The register may be written using a data write operation to a dedicated region of memory. Several modules, such as a processor or a DMA module, may be able to write to the register via separate access ports. The cache may be a level 2 cache. The cache may have cache lines 5 in a data memory 3 and corresponding tags 9 in a data memory 7. It may also have a cache load circuit 19.

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