公开(公告)号：DE69932917D1

公开(公告)日：2006-10-05

申请号：DE69932917

申请日：1999-04-09

Applicant: ST MICROELECTRONICS NV

Inventor： APPELTANS KOEN ,  BOXHO JEAN ,  MACQ DAMIEN LUC FRANCOIS ,  VANDERBAUWHEDE WIM

IPC: H01G4/30 ,  H01G4/38 ,  H01L23/522 ,  H01L27/08

Abstract: A layered capacitor device with high capacitance per unit area is realised by alternating in the vertical direction first layers (FL1, FL2, FL3, FL4, FL5) and second layers (SL1, SL2, SL3, SL4). A first layer (FL2) consists of horizontally alternating electrically conducting tracks (T2,2; T2,3) and electrically insulating tracks, whereas a second layer consists of electrically insulating material, e.g. an oxide. In this way top-bottom capacitors (CTB) and side-wall capacitors (CSW) are constituted that are parallel coupled to form the layered capacitor device. In a preferred embodiment of the invention, this parallel coupling is realised by conductively interconnecting diagonally neighbouring electrically conducting tracks (T1,2; T2,3).

公开(公告)号：AT337606T

公开(公告)日：2006-09-15

申请号：AT99400876

申请日：1999-04-09

Applicant: ST MICROELECTRONICS NV

Inventor： APPELTANS KOEN ,  BOXHO JEAN ,  MACQ DAMIEN LUC FRANCOIS ,  VANDERBAUWHEDE WIM

IPC: H01G4/30 ,  H01G4/38 ,  H01L23/522 ,  H01L27/08

Abstract: A layered capacitor device with high capacitance per unit area is realised by alternating in the vertical direction first layers (FL1, FL2, FL3, FL4, FL5) and second layers (SL1, SL2, SL3, SL4). A first layer (FL2) consists of horizontally alternating electrically conducting tracks (T2,2; T2,3) and electrically insulating tracks, whereas a second layer consists of electrically insulating material, e.g. an oxide. In this way top-bottom capacitors (CTB) and side-wall capacitors (CSW) are constituted that are parallel coupled to form the layered capacitor device. In a preferred embodiment of the invention, this parallel coupling is realised by conductively interconnecting diagonally neighbouring electrically conducting tracks (T1,2; T2,3).