公开(公告)号：DE602006007778D1

公开(公告)日：2009-08-27

申请号：DE602006007778

申请日：2006-08-29

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： ISANI SONIYA T ,  RADHAKRISHNAN HARIHARASUDHAN K

IPC: G06F13/28 ,  G06F13/42

Abstract: The present invention provides an area efficient system for providing serial access of multiple data buffers to a data retaining and processing device, comprising a signal synchronization and detection means for synchronizing a clock signal and a data signal, a shifting means for receiving and retaining data received from said data bus to thereby generate a status signal indicating the receipt of data; a reference bus address and said data bus. A comparing means is also provided for comparing said reference bus address with the content of said storage means for generating an address matching signal and a control signal generation means for generating control signals to govern the data write signal generation for said shifting means. A sequencing means for reading data from said data retaining and processing device and a direct storage access (DMA) controlling means for generating interrupt signals, access request signals.