公开(公告)号：JP2003124809A

公开(公告)日：2003-04-25

申请号：JP2002283854

申请日：2002-09-27

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： NANDY TAPAS

IPC: H03M1/10 ,  H03M1/08 ,  H03M1/38 ,  H03M1/46 ,  H03M1/80

Abstract: PROBLEM TO BE SOLVED: To provide a switched capacitor charge redistribution sequential approximation type analog-to-digital converter which neither greatly increases in circuit scale nor increases conversion time while its quantization error is uniformly distributed between +0.5LSB and -0.5LSB. SOLUTION: Disclosed is an improved binary weighted switched capacitor charge redistribution sequential approximation type analog-to-digital converter (ADC), which is equipped with a mechanism for adding electric charges corresponding to the least significant digit bit (LSB) of the ADC to electric charges accumulated in a switched capacitor after the sampling stage of the ADC, thereby providing the quantization error which is uniformly distributed between +0.5LSB and -0.5LSB without requiring any additional processing clock cycle.

公开(公告)号：DE602005003309T2

公开(公告)日：2008-09-04

申请号：DE602005003309

申请日：2005-12-02

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： JAISINGHANI POOJA ,  NANDY TAPAS

IPC: G06F1/28 ,  G01R19/165 ,  G06F1/26 ,  G11C16/30

公开(公告)号：DE602004009137D1

公开(公告)日：2007-11-08

申请号：DE602004009137

申请日：2004-07-28

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： NANDY TAPAS

IPC: H03K7/06 ,  H03K5/1252 ,  H03K5/13 ,  H03K7/04 ,  H04B15/04 ,  H04L7/00 ,  H04L25/00

Abstract: The present invention provides a digital clock modulator providing a smoothly modulated clock period to reduce emitted Electro-Magnetic Radiation (EMR) comprising a plurality of delay elements (14) connected in series receiving an unmodulated clock signal at the input, connected to a multiplexer (11) receiving inputs from unequally spaced selected taps provided between the delay elements. A control block (12) supplies the selection-inputs to said multiplexer (11), and receives a clock signal from said series of delay elements. Further, a predetermined delay element (13) is connected between the clock terminal of the said control block (12) and the last element U(n) of said series of delay elements for enabling glitch free operation by ensuring that the entire delay chain and related signal paths are in the same stable state before the control to the multiplexer changes.

公开(公告)号：DE602004009137T2

公开(公告)日：2008-06-19

申请号：DE602004009137

申请日：2004-07-28

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： NANDY TAPAS

IPC: H03K7/06 ,  H03K5/1252 ,  H03K5/13 ,  H03K7/04 ,  H04B15/04 ,  H04L7/00 ,  H04L25/00

Abstract: The present invention provides a digital clock modulator providing a smoothly modulated clock period to reduce emitted Electro-Magnetic Radiation (EMR) comprising a plurality of delay elements (14) connected in series receiving an unmodulated clock signal at the input, connected to a multiplexer (11) receiving inputs from unequally spaced selected taps provided between the delay elements. A control block (12) supplies the selection-inputs to said multiplexer (11), and receives a clock signal from said series of delay elements. Further, a predetermined delay element (13) is connected between the clock terminal of the said control block (12) and the last element U(n) of said series of delay elements for enabling glitch free operation by ensuring that the entire delay chain and related signal paths are in the same stable state before the control to the multiplexer changes.

公开(公告)号：DE602005003309D1

公开(公告)日：2007-12-27

申请号：DE602005003309

申请日：2005-12-02

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： JAISINGHANI POOJA ,  NANDY TAPAS

IPC: G06F1/28 ,  G01R19/165 ,  G06F1/26 ,  G11C16/30