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公开(公告)号：DE602005020218D1
公开(公告)日：2010-05-12
申请号：DE602005020218
申请日：2005-07-28
Applicant: ST MICROELECTRONICS PVT LTD
Inventor： SAHA KAUSHIK , SARKAR ABHIK , MAITI SRIJIB NARAYAN
Abstract: A macro-block level parallel implementation of a video decoder in parallel processing environment comprising a Variable Length Decoding (VLD) block to decode the encoded Discrete Cosine Transform (DCT) coefficient; a master node which receives said decoded Discrete Cosine Transform (DCT) coefficients; and, plurality of slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at macro-block level.
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