公开(公告)号：GB2521121A

公开(公告)日：2015-06-17

申请号：GB201319683

申请日：2013-11-07

Applicant: ST MICROELECTRONICS RES & DEV ,  ST MICROELECTRONICS GRENOBLE 2

Inventor： SARTA DAVIDE ,  URZI IGNAZIO-ANTONINO

IPC: G06F13/24

Abstract: A method comprises: capturing a set of interrupts; and outputting them serially onto an interconnect for routing to a destination. Only active interrupts may be output. Interrupts may be processed before output, and an interrupt status register may be updated each time an interrupt has been processed. While a first set of interrupts is being processed, a second set of interrupts may be being captured. The processing may comprise packetizing, and may comprise information about a type, destination, an interrupt level, or routing information. The interconnect may comprise a network on chip 208, 210, 212, 214. The packetized interrupt may be de-packetized or unpacked at the destination. Using an existing interconnect obviates the need for a complex arrangement of interrupt lines (Figure 3) which might otherwise occupy a significant silicon area.

公开(公告)号：GB2495543A

公开(公告)日：2013-04-17

申请号：GB201117766

申请日：2011-10-14

Applicant: ST MICROELECTRONICS RES & DEV

Inventor： SARTA DAVIDE ,  SMITH DAVID

IPC: G06F9/48 ,  G06F13/24

Abstract: A routing architecture for routing interrupt requests (IRQ) receives m inputs, irq_in, and outputs n output request signals, irq_out. Shift register 18 receives m inputs and is configured such that k bits are shifted down in one cycle, where m is greater than k. The k bits of shift register 18 are provided to routing arrangement or multiplexer 20, e.g. a full combinatorial k x n cross bar, which provides n outputs to an output logic register 28 comprising set logic. Routing arrangement 20 is configured to perform a plurality of cycles to provide said set of n output request signals. Shift register 18 has to be shifted m/k times, meaning that m/k cycles are required for routing arrangement 20 to produce n outputs. Accordingly, instead of a large routing arrangement in one step, a smaller routing arrangement 20 is used a plurality of times. The routing architecture also includes, inverters 10, mask 12, synchronisation register 14 and a controller FSM (finite state machine) 26. The invention may be used with any suitable requests, e.g. direct memory access (DMA) requests, status requests, and/or service requests.

公开(公告)号：GB2495533A

公开(公告)日：2013-04-17

申请号：GB201117706

申请日：2011-10-13

Applicant: ST MICROELECTRONICS RES & DEV

Inventor： SARTA DAVIDE

IPC: G06F12/06 ,  G06F13/16

Abstract: A memory management unit is connected to several memory devices. When a buffer is allocated to the memory devices, the buffer is divided up into slices and the slices are allocated to the different devices, such that a substantially equal number of slices are allocated to each device. The slices may be allocated to the devices on a rotating basis. The slices may be the same size as a page of memory. The memory management unit may manipulate the addresses supplied to the unit by swapping bits, in order to allocate the buffers to the different devices. The memory management unit may be part of a system-on-chip integrated circuit. The memory management unit may be connected to double data rate (DDR) memories.