公开(公告)号：EP1835621B1

公开(公告)日：2010-09-01

申请号：EP07104178.4

申请日：2007-03-14

Applicant: ST MICROELECTRONICS S.A.

Inventor： Rieubon, Sébastien ,  Kraemer, Michael

IPC: H03K21/40

CPC classification number: H03K21/406

公开(公告)号：EP1835621A1

公开(公告)日：2007-09-19

申请号：EP07104178.4

申请日：2007-03-14

Applicant: ST MICROELECTRONICS S.A.

Inventor： Rieubon, Sébastien ,  Kraemer, Michael

IPC: H03K21/40

CPC classification number: H03K21/406

Abstract: The invention concerns counting circuitry for providing a corrected count value based on the number of rising and falling edges of an input signal occurring during a reference time period, the counting circuitry comprising a counter (22) arranged to provide a first count value based on one of the number of said rising edges of said input signal occurring during said reference time period, and the number of said falling edges of said input signal occurring during said reference time period; characterised in that said counting circuitry further comprises adjustment circuitry (24-26) arranged to generate a corrected count value by determining the state of said input signal at the start time (70) and end time (72) of said reference time period, and adjusting said first count value if the state of said input signal at the start of said reference time period is different from the state of said input signal at the end of said reference time period.

Abstract translation: 本发明涉及用于基于在参考时间段期间发生的输入信号的上升沿和下降沿的数量来提供校正的计数值的计数电路，该计数电路包括计数器（22），其被布置为基于一个第一计数值 在所述参考时间段期间发生的所述输入信号的所述上升沿的数量以及在所述参考时间段期间发生的所述输入信号的所述下降沿的数量; 其特征在于，所述计数电路还包括调整电路（24-26），其被布置成通过在所述参考时间段的开始时间（70）和结束时间（72）确定所述输入信号的状态来产生校正的计数值，以及 如果所述参考时间段开始时的所述输入信号的状态与所述参考时间段结束时所述输入信号的状态不同，则调整所述第一计数值。