公开(公告)号：JP2003229755A

公开(公告)日：2003-08-15

申请号：JP2002261496

申请日：2002-09-06

Applicant: ST MICROELECTRONICS SA

Inventor： CARANANA JOEL

IPC: G06F3/00 ,  G06F13/40 ,  H03K5/151 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To provide a control circuit for controlling serial cables having approximately the same rise and decay times. SOLUTION: A bus interface comprises a first circuit, based on a first pair of transistors (10 and 20) of opposite types, having control electrode and a common electrode provided with a first output potential (D+). A second circuit comprises a second pair of transistors (30 and 40) of opposite types, having a common electrode for providing a second potential (D-) by switching in opposite direction from the former. This device comprises first capacitive coupling means for feeding a portion of the signal existing at the first potential (D+) back into the control electrode at the second transistor pair and second capacitive coupling means for feeding a portion of the signal existing at the second potential (D-) back into the control electrodes of the first transistor pair. COPYRIGHT: (C)2003,JPO

公开(公告)号：FR2829599A1

公开(公告)日：2003-03-14

申请号：FR0111567

申请日：2001-09-07

Applicant: ST MICROELECTRONICS SA

Inventor： CARANANA JOEL

IPC: G06F13/40 ,  H03K5/151 ,  G06F3/00 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175 ,  G06F13/10

Abstract: Bus interface comprises a first circuit based on a first pair of transistors (10, 20), of opposing type (N or P type), forming a driver electrode with a common output potential (D+). A second circuit comprises transistors (30, 40) of opposing type with a common output potential (D-). The two circuits are coupled such that the signal at the first potential is partially linked to the second potential. The shift in rise and fall times of the two potentials is thus compensated.