公开(公告)号：JP2000353712A

公开(公告)日：2000-12-19

申请号：JP2000137263

申请日：2000-05-10

Applicant: ST MICROELECTRONICS SA

Inventor： JOSSE EMILE

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/50

Abstract: PROBLEM TO BE SOLVED: To obtain the packaging method of a chip formed on a semiconductor wafer with an electrically contacting part on both surfaces. SOLUTION: This packaging method contains a stage, where a conductive region 8 is provided on the first surface of a wafer, a stage where the first thick plate 10 of electric insulating material is adhered to the first surface, a stage where the wafer is etched from the second surface of the wafer with which a chip is prescribed, a stage where the conductive track 12, extending from the contact part 11 of the second surface to a conductive region is deposited, a stage where the second surface is covered by the second thick plate 14 and a fixing cap is formed by an insulating filling material 13 between the first thick plate and the second thick plate, and a stage where the conductive material, extending in track form to the surface of the first thick plate, is deposited on the conductive region.

公开(公告)号：FR2793605B1

公开(公告)日：2001-07-27

申请号：FR9906244

申请日：1999-05-12

Applicant: ST MICROELECTRONICS SA

Inventor： JOSSE EMILE

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/50 ,  H01L23/06 ,  H01L21/52 ,  H01L23/485

Abstract: The casing of semiconductor chip, implementing e.g. Zener diode, made of semiconductor e.g. silicon wafer comprises the following stages: the provision of conducting zone (8) on the first side of wafer extending over the periphery of chip to be formed; the bonding by an adhesive of a thick plate (10) made of electrically insulating material, e.g. glass of thickness 200-500 micrometer, to the first side of wafer; the etching of wafer on the second side to define the chip. The deposition of at least one conducting track (12) extending over the contact zone of substrate (11) on the second side of chip; the covering of the second side of chip by a thick plate (14), made of e.g. silicon of thickness 200-800 micrometer, with the interposition of an insulating material (13) as e.g. epoxy resin, between the first and second plates; and the etching of the first plate at least in the conducting zone for the deposition of conducting material extended in the form of tracks (17,18) on the free surface. The method also includes the final stage of cutting to separate obtained casings. The first plate (10) is thinned before laying on conducting zone (8), and the second side of wafer is thinned before the etching stage for defining the chip. The thickness of second plate (14) is chosen as a function of mechanical properties required of casing. The etching of the first plate (10) is carried out according to a pattern forming two plots (20,21). The extension of contact from the conducting zone (8) is effected in the zone of separation of two plots. The second plate (14) can also be made of an insulating material, or at least partly of a thermally conducting material.

公开(公告)号：DE60000304D1

公开(公告)日：2002-09-12

申请号：DE60000304

申请日：2000-05-11

Applicant: ST MICROELECTRONICS SA

Inventor： JOSSE EMILE

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/50

Abstract: The casing of semiconductor chip, implementing e.g. Zener diode, made of semiconductor e.g. silicon wafer comprises the following stages: the provision of conducting zone (8) on the first side of wafer extending over the periphery of chip to be formed; the bonding by an adhesive of a thick plate (10) made of electrically insulating material, e.g. glass of thickness 200-500 micrometer, to the first side of wafer; the etching of wafer on the second side to define the chip. The deposition of at least one conducting track (12) extending over the contact zone of substrate (11) on the second side of chip; the covering of the second side of chip by a thick plate (14), made of e.g. silicon of thickness 200-800 micrometer, with the interposition of an insulating material (13) as e.g. epoxy resin, between the first and second plates; and the etching of the first plate at least in the conducting zone for the deposition of conducting material extended in the form of tracks (17,18) on the free surface. The method also includes the final stage of cutting to separate obtained casings. The first plate (10) is thinned before laying on conducting zone (8), and the second side of wafer is thinned before the etching stage for defining the chip. The thickness of second plate (14) is chosen as a function of mechanical properties required of casing. The etching of the first plate (10) is carried out according to a pattern forming two plots (20,21). The extension of contact from the conducting zone (8) is effected in the zone of separation of two plots. The second plate (14) can also be made of an insulating material, or at least partly of a thermally conducting material.

公开(公告)号：FR2793605A1

公开(公告)日：2000-11-17

申请号：FR9906244

申请日：1999-05-12

Applicant: ST MICROELECTRONICS SA

Inventor： JOSSE EMILE

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/50 ,  H01L23/06 ,  H01L21/52 ,  H01L23/485

Abstract: The casing of semiconductor chip, implementing e.g. Zener diode, made of semiconductor e.g. silicon wafer comprises the following stages: the provision of conducting zone (8) on the first side of wafer extending over the periphery of chip to be formed; the bonding by an adhesive of a thick plate (10) made of electrically insulating material, e.g. glass of thickness 200-500 micrometer, to the first side of wafer; the etching of wafer on the second side to define the chip. The deposition of at least one conducting track (12) extending over the contact zone of substrate (11) on the second side of chip; the covering of the second side of chip by a thick plate (14), made of e.g. silicon of thickness 200-800 micrometer, with the interposition of an insulating material (13) as e.g. epoxy resin, between the first and second plates; and the etching of the first plate at least in the conducting zone for the deposition of conducting material extended in the form of tracks (17,18) on the free surface. The method also includes the final stage of cutting to separate obtained casings. The first plate (10) is thinned before laying on conducting zone (8), and the second side of wafer is thinned before the etching stage for defining the chip. The thickness of second plate (14) is chosen as a function of mechanical properties required of casing. The etching of the first plate (10) is carried out according to a pattern forming two plots (20,21). The extension of contact from the conducting zone (8) is effected in the zone of separation of two plots. The second plate (14) can also be made of an insulating material, or at least partly of a thermally conducting material.