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    EEPROM COMPRISING A NON-VOLATILE REGISTER WHICH IS INTEGRATED INTO THE MEMORY AREA THEREOF
    1.
    发明申请
    EEPROM COMPRISING A NON-VOLATILE REGISTER WHICH IS INTEGRATED INTO THE MEMORY AREA THEREOF 审中-公开
    包含一个非易失性寄存器的EEPROM集成到其内存区域

    公开(公告)号：WO2004021361A3

    公开(公告)日：2004-07-29

    申请号：PCT/FR0302559

    申请日：2003-08-21

    Applicant: ST MICROELECTRONICS SA ,  LA ROSA FRANCESCO

    Inventor： LA ROSA FRANCESCO

    IPC: G11C16/04 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/20

    CPC classification number: H01L27/11521 ,  G11C16/0441 ,  H01L27/115 ,  H01L27/11524

    Abstract: The invention relates to an electrically erasable programmable memory which is integrated onto a silicon substrate, comprising a memory area consisting of normal bit lines (BLj) and normal memory cells (C(i, j)) which are connected to the aforementioned normal bit lines (BLj). Each normal memory cell consists of a floating gate transistor (FGT) comprising a tunnel window (TW) and a selection transistor (ST). According to the invention, the memory area (MA) includes at least one memory point of a non-volatile register (NVREG), comprising: a normal memory cell (C(i+1, j) which is connected to a normal bit line (BLj) of the memory area and which can be erased and programmed using decoders (RDEC, CDEC) of the memory area; a special memory cell C(i+1, j+1) comprising a floating gate transistor (FGT) without a tunnel window, the floating gate of the floating gate transistor of the special memory cell being connected to the floating gate of the floating gate transistor of the normal memory cell; and a special bit line (RBL+1) which is used to connect the special memory cell of the memory point to a specific read-out circuit of the memory point.

    Abstract translation: 本发明涉及一种电可擦除可编程存储器，其集成在硅衬底上，包括由正常位线（BLj）和正常存储单元（C（i，j））组成的存储区域，其连接到上述正常位线 （BLJ）的。 每个正常存储单元由包括隧道窗（TW）和选择晶体管（ST）的浮栅晶体管（FGT）组成。 根据本发明，存储区（MA）包括非易失性寄存器（NVREG）的至少一个存储点，包括：正常存储器单元（C（i + 1，j），其连接到正常位线 （BLj），并且可以使用存储器区域的解码器（RDEC，CDEC）来擦除和编程;特殊存储单元C（i + 1，j + 1），包括不具有 特殊存储单元的浮栅晶体管的浮栅与正常存储单元的浮栅晶体管的浮置栅极相连，特殊位线（RBL + 1）用于连接特殊存储单元 存储器的存储单元指向存储点的特定读出电路。

    EEPROM CHARGE RETENTION CIRCUIT FOR TIME MEASUREMENT
    2.
    发明申请
    EEPROM CHARGE RETENTION CIRCUIT FOR TIME MEASUREMENT 审中-公开
    EEPROM充电保持电路，用于时间测量

    公开(公告)号：WO2008012464A2

    公开(公告)日：2008-01-31

    申请号：PCT/FR2007051705

    申请日：2007-07-20

    Applicant: ST MICROELECTRONICS SA ,  LA ROSA FRANCESCO

    Inventor： LA ROSA FRANCESCO

    IPC: G11C16/26

    CPC classification number: G11C16/22 ,  G04F10/10 ,  G11C16/0441 ,  G11C16/26

    Abstract: The invention relates to an electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each comprising a selection transistor in series with a floating-gate transistor, the circuit comprising, on any one row of memory cells: a first subassembly of at least a first cell (C1), the thickness of the dielectric of the tunnel window of the floating-gate transistor of which is less than that of the other cells; a second subassembly of at least a second cell (C2), the drain and source of the floating-gate transistor of which are interconnected; a third subassembly of at least a third cell (7); and a fourth subassembly of at least a fourth cell (6), the tunnel window of which is omitted, the respective floating gates of the transistors of the cells of the four subassemblies being interconnected.

    Abstract translation: 本发明涉及一种用于时间测量的电子电荷保持电路，其被注入到一个EEPROM存储单元的阵列中，每个EEPROM存储单元包括与浮置栅极晶体管串联的选择晶体管，该电路在任何一行存储单元上包括：第一 至少第一单元（C1）的子组件，其浮栅晶体管的隧道窗口的电介质的厚度小于其它单元的电介质的厚度; 至少第二单元（C2）的第二子组件，其浮置晶体管的漏极和源极相互连接; 至少第三电池（7）的第三子组件; 以及至少第四单元（6）的第四子组件，其通道窗口被省略，四个子组件的单元的晶体管的相应浮动栅互连。

    PROGRAMMING OF A CHARGE RETENTION CIRCUIT FOR TIME MEASUREMENT
    3.
    发明申请
    PROGRAMMING OF A CHARGE RETENTION CIRCUIT FOR TIME MEASUREMENT 审中-公开
    用于时间测量的充电保持电路的编程

    公开(公告)号：WO2008012463A2

    公开(公告)日：2008-01-31

    申请号：PCT/FR2007051701

    申请日：2007-07-20

    Applicant: ST MICROELECTRONICS SA ,  LA ROSA FRANCESCO

    Inventor： LA ROSA FRANCESCO

    IPC: G11C27/02

    CPC classification number: G11C27/024 ,  G04F10/10 ,  G11C27/005

    Abstract: The invention relates to a method of controlling an electronic charge retention circuit for time measurement, comprising at least a first capacitive element (C1), the dielectric of which has a leakage, and at least a second capacitive element (C2), the dielectric of which has a higher capacitance than the first, the two elements having a common electrode defining a floating node (F) that can be connected to an element (5) for measuring its residual charge, in which a charge retention period is programmed or initialized by injecting or extracting charges via the first element.

    Abstract translation: 本发明涉及一种控制用于时间测量的电子电荷保持电路的方法，该方法至少包括其电介质具有泄漏的第一电容元件（C1）和至少第二电容元件（C2） 其具有比第一电容高的电容，所述两个元件具有限定浮动节点（F）的公共电极，该电极可以连接到用于测量其剩余电荷的元件（5），其中电荷保持周期被编程或初始化 通过第一元素注入或提取电荷。

    CIRCUIT FOR READING A CHARGE RETENTION ELEMENT FOR TEMPORAL MEASUREMENT
    4.
    发明申请
    CIRCUIT FOR READING A CHARGE RETENTION ELEMENT FOR TEMPORAL MEASUREMENT 审中-公开
    读取用于时间测量的充电保持元件的电路

    公开(公告)号：WO2008012462A3

    公开(公告)日：2008-04-03

    申请号：PCT/FR2007051700

    申请日：2007-07-20

    Applicant: ST MICROELECTRONICS SA ,  LA ROSA FRANCESCO

    Inventor： LA ROSA FRANCESCO

    IPC: G11C27/00 ,  G11C7/10

    CPC classification number: G11C7/06 ,  G04F10/10 ,  G11C7/062

    Abstract: The invention relates to a method and a circuit for reading an electronic charge retention element (10) for a temporal measurement, of the type comprising at least one capacitive element (C1, C2) whose dielectric exhibits a leakage and a transistor with insulated control terminal (5) for reading the residual charges, the reading circuit comprising: two parallel branches between two supply terminals, each branch comprising at least one transistor of a first type (P1, P2) and one transistor of a second type (N3, 5), the transistor of the second type of one of the branches consisting of that of the element to be read and the transistor of the second type of the other branch receiving, on its control terminal, a staircase signal (VDAC), the respective drains of the transistors of the first type being connected to the respective inputs of a comparator (135) whose output (OUT) provides an indication of the residual voltage in the charge retention element.

    Abstract translation: 本发明涉及一种用于读取用于时间测量的电子电荷保持元件（10）的方法和电路，其类型包括其电介质呈现泄漏的至少一个电容元件（C1，C2）和具有绝缘控制端子的晶体管 （5）用于读取剩余电荷，所述读取电路包括：两个电源端之间的两个并联支路，每个支路包括至少一个第一类型的晶体管（P1，P2）和一个第二类型晶体管（N3,5） ，第二类型的一个分支的晶体管由待读取的元件的晶体管和第二类型的另一支路的晶体管在其控制端子上接收一个阶梯信号（VDAC），相应的漏极 第一类型的晶体管连接到比较器（135）的相应输入，其比较器（135）的输出（OUT）提供电荷保留元件中的残余电压的指示。

    CHARGE RETENTION CIRCUIT FOR TIME MEASUREMENT
    5.
    发明申请
    CHARGE RETENTION CIRCUIT FOR TIME MEASUREMENT 审中-公开
    充电保持电路用于时间测量

    公开(公告)号：WO2008012459A3

    公开(公告)日：2008-03-13

    申请号：PCT/FR2007051696

    申请日：2007-07-20

    Applicant: ST MICROELECTRONICS SA ,  LA ROSA FRANCESCO

    Inventor： LA ROSA FRANCESCO

    IPC: G11C27/02

    CPC classification number: G11C27/005 ,  G04F10/10 ,  G11C27/024

    Abstract: The invention relates to an electronic charge retention circuit for time measurement, comprising: at least a first capacitive element (C1), a first electrode (21) of which is connected to a floating node (F); at least a second capacitive element (C2), a first electrode (31) of which is connected to said floating node (F), the first capacitive element having a leakage through its dielectric space (23) and the second capacitive element having a capacitance greater than the first; and at least a first transistor (5) having an isolated control terminal connected to said floating node.

    Abstract translation: 本发明涉及一种用于时间测量的电子电荷保持电路，包括：至少第一电容元件（C1），其第一电极（21）连接到浮动节点（F）; 至少第二电容元件（C2），其第一电极（31）连接到所述浮动节点（F），所述第一电容元件通过其介电空间（23）具有泄漏，所述第二电容元件具有电容 大于第一; 以及具有连接到所述浮动节点的隔离控制端的至少第一晶体管（5）。

    9.
    发明专利
    未知

    公开(公告)号：DE60042634D1

    公开(公告)日：2009-09-10

    申请号：DE60042634

    申请日：2000-11-22

    Applicant: ST MICROELECTRONICS SA

    Inventor： LA ROSA FRANCESCO

    IPC: H03M13/19 ,  G06F11/10 ,  G11C29/00

    Abstract: The error correction procedure corrects an error in bit b2 in a sequence of bits b0 - b8. A parity bit (b8) is calculated from the other bits b1 - b7 at an instant where the erroneous bit (b2) was valid, and a second parity bit (b9) calculated from all the bits except the erroneous bit, to replace the erroneous bit.

    EEPROM has separate simultaneously readable condition and configuration bit lines
    10.
    发明专利
    EEPROM has separate simultaneously readable condition and configuration bit lines 未知

    公开(公告)号：FR2831315A1

    公开(公告)日：2003-04-25

    申请号：FR0113635

    申请日：2001-10-22

    Applicant: ST MICROELECTRONICS SA

    Inventor： LA ROSA FRANCESCO

    IPC: G11C16/20 ,  G11C16/02

    Abstract: An EEPROM (Electrically Erasable PROgrammable Memory) memory has a column (COL0) with special zones for condition and configuration bits of N1 (BL5-BL7) and N2 (BL0-BL4) separated bit lines connected respectively to the cells in one zone, and not to cells in the other zone. An Independent claim is also included for a process for storing and reading special bits of a first type and of a second type in an electrically erasable and programmable memory.

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