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    MPEG DECODING CIRCUIT FOR DISPLAYING PICTURE AND NOTICE PICTURE
    1.
    发明专利
    MPEG DECODING CIRCUIT FOR DISPLAYING PICTURE AND NOTICE PICTURE 失效

    公开(公告)号：JP2001197494A

    公开(公告)日：2001-07-19

    申请号：JP2000335825

    申请日：2000-11-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY PIERRE

    IPC: H04N5/265 ,  G06T9/00 ,  H03M7/30 ,  H04N5/45 ,  H04N7/26 ,  H04N7/50 ,  H04N7/24

    Abstract: PROBLEM TO BE SOLVED: To decode and display a main picture and a notice picture by using a single MPEG decoder and a memory. SOLUTION: In a circuit 12, a memory 6 is connected to a bus 8 to be accessed from a bidirectional bus 8, an MEPG decoder 4 is connected to the bus 8 to read encoding and decoding data of the memory and an encoded data output part is arranged, which is connected to the bus along a first path 16, by which reading is performed from the memory data of a first picture. A first picture display circuit 10 is connected to the bus to permit its input part to read data written by a decoder from the memory, a decimeter circuit 14 and a second picture display circuit 18 are included, the decimeter circuit is connected to a part between the output part of the decoder and the bus along a second path to write the second picture data displayed by reduction in the memory and, then, a second picture display circuit is connected to the bus to read data written by the decimeter circuit from the memory.

    MPEG DECODER USING COMMON USE MEMORY
    2.
    发明专利
    MPEG DECODER USING COMMON USE MEMORY 失效

    公开(公告)号：JP2001189935A

    公开(公告)日：2001-07-10

    申请号：JP2000335824

    申请日：2000-11-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： MOUTIN JEAN MICHEL ,  MARTY PIERRE

    IPC: G06F12/00 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  H04N7/24

    Abstract: PROBLEM TO BE SOLVED: To properly provide a priority of a common memory, when an MPEG decoder and microcomputer use the common memory. SOLUTION: The MPEG decoder includes a microprocessor, decoder that decodes an image sequence, memory in common use with the microprocessor and the decoder, circuit that evaluates a delay in the decoder, and control circuit that gives memory access priority to the decoder, when the delay in the decoder is higher than a prescribed level or gives the memory access priority to the microprocessor when it is not.

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