公开(公告)号：JP2001210656A

公开(公告)日：2001-08-03

申请号：JP2000390445

申请日：2000-12-22

Applicant: ST MICROELECTRONICS SA

Inventor： MATHIEU ROY

IPC: H01L21/332 ,  H01L21/225 ,  H01L21/331 ,  H01L21/76 ,  H01L21/761 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a vertical power element on a substrate formed of a lightly-doped silicon wafer. SOLUTION: Vertical holes are made on the surface of a lower side of the substrate. A second conductive type dopant which is opposite to the substrate is diffused from the holes. Similar holes are made on the surface of the upper side of the substrate, an isolating wall is regulated and second conductive type dopant which is heavily doped from the hole is diffused. The holes corresponding to the isolating wall are sufficiently close to a diffusion area, and they are connected in the lateral direction and the vertical direction.

公开(公告)号：JP2000200909A

公开(公告)日：2000-07-18

申请号：JP36690699

申请日：1999-12-24

Applicant: ST MICROELECTRONICS SA

Inventor： JEAN JALADE ,  JEAN-LOUIS SANCHEZ ,  LAUR JEAN-PIERRE ,  BREIL MARIE ,  AUSTIN PATRICK ,  BERNIER ERIC ,  MATHIEU ROY

IPC: H01L29/74 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L29/739 ,  H01L29/78 ,  H01L21/06

Abstract: PROBLEM TO BE SOLVED: To obtain a part of a minimum surface to a fixed maximum current by checking a thyristor type part. SOLUTION: An auxiliary thyristor 13 is a vertical thyristor, and a cathode corresponds to an N-type region N5 formed in a well likewise. A part of a region P4 between regions N4 and N5 is covered with an insulation gate G2 and regions N4-P4-N5 corresponds to an N-channel enhancement MOS transistor M. An IGBT 14 is made a multicellor part. When the surface of a rear is covered with a P-type layer P1, a vertical IGBT is formed, and a cathode corresponds to metallization formed on regions P6, N6 and an anode corresponds to a surface at a rear side of a part. For a cell corresponding to a well P6, conduction takes place starting from an anode A towards metallization which covers the source N6, and the region N5 and then towards the region N4 and a cathode K. Next, conduction of a thyristor is checked.

公开(公告)号：JP2002270812A

公开(公告)日：2002-09-20

申请号：JP2001146544

申请日：2001-05-16

Applicant: ST MICROELECTRONICS SA

Inventor： MATHIEU ROY

IPC: H01L21/331 ,  H01L23/31 ,  H01L29/06 ,  H01L29/417 ,  H01L29/732 ,  H01L29/74

Abstract: PROBLEM TO BE SOLVED: To provide the peripheral structure of a power component resisting a high voltage. SOLUTION: A power component formed in an N-type silicon substrate, the lower and upper surfaces of which respectively include a first and a second P-type region, that does not extend to the component periphery, the high voltage being capable of existing between the first and second regions and having to withstand the junctions between the first and second regions and the substrate. A deep insulating region 31 that does not join the first region 3 is provided at the lower periphery of the component. The lower surface of the substrate between the deep insulating region and the first region is coated with an insulating-layer. The height of the deep insulating region is greater than the upward extension of soldering 22, formed during the soldering of the lower surface on a heat sink.

公开(公告)号：JP2000124472A

公开(公告)日：2000-04-28

申请号：JP29533399

申请日：1999-10-18

Applicant: ST MICROELECTRONICS SA

Inventor： MATHIEU ROY

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/861

Abstract: PROBLEM TO BE SOLVED: To restrain a trouble generated by breakdown voltage of a power constituent part when a mutual connection track exists. SOLUTION: The power constituent part is formed in an N-type silicon board defined by a P-type wall surface and has a lower surface including a first P-type region 3 connected to the wall surface, an upper surface including a second P-type region and a conductive layer extending between the second region 4, and a wall surface on a board. The constituent part includes a third N-type region 22 of high doping level formed under a layer part which is almost in a middle between an outer circumferential edge part of the second region 4 and an inner circumferential edge part of a wall surface in a substrate 1. The third region 22 is in contact with a filed plate 21 which extends in both sides of the third region 22 in the direction of a wall surface and the direction of the third region 22.