公开(公告)号：FR2801719B1

公开(公告)日：2002-03-01

申请号：FR9915114

申请日：1999-11-30

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  VARISCO LAURA

IPC: G11C7/08 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28

Abstract: A device for reading a memory including precharging circuits for precharging the inputs of a differential amplifier to a precharging voltage. The precharging voltage may be at an intermediate voltage level between a precharging voltage level of the bit lines and the voltage level of the logic supply voltage. This provides for a very fast build-up, during a following evaluation phase, of the output of the amplifier in a state corresponding to that of the cell being read. An internal detection circuit may also be included to detect an end of the precharging to stop the precharging circuit and activate the read current generator for the evaluation phase.

公开(公告)号：FR2803456B1

公开(公告)日：2003-01-17

申请号：FR9916818

申请日：1999-12-31

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  VARISCO LAURA

IPC: H01L27/088 ,  H01L29/423 ,  H03K19/003 ,  H03K19/0944 ,  H03K17/56 ,  G11C16/12

公开(公告)号：FR2803456A1

公开(公告)日：2001-07-06

申请号：FR9916818

申请日：1999-12-31

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  VARISCO LAURA

IPC: H01L27/088 ,  H01L29/423 ,  H03K19/003 ,  H03K19/0944 ,  H03K17/56 ,  G11C16/12

Abstract: The high voltage switch has first circuit branch with high voltage field effect transistor and a resistance. There is a second parallel branch with two field effect transistors connected in series. The lower of these is a high voltage type, and the switch output is taken from the connection between these two transistors. The higher voltage switch comprises a first branch with a resistor (R) and a first MOS transistor of n-type (HT1) connected in series, and a second branch with two MOS transistors of n-type (HT2,HT3) connected in series, where both branches are connected between the higher voltage node (N1) and the ground. The connection point (B) between the second and third transistors gives the output signal (Out), and the second transistor (HT2) is controlled by the gate connected to the connection point (A) between the resistor (R), e.g. 20 kOhm, and the first transistor (HT1). The transistors are higher voltage MOS transistors of drift type with the drain formed by a structure with a well region and field oxide, or floating-gate type which is used as the control gate and comprises an oxide tunnel and gradual junction.

公开(公告)号：FR2801719A1

公开(公告)日：2001-06-01

申请号：FR9915114

申请日：1999-11-30

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  VARISCO LAURA

IPC: G11C7/08 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28

Abstract: The reading device comprises a differential amplifier (2) with inputs (MTX, REF) each connected to the output (SR, SD) of respective current-voltage converter (CIVD, CIVR), whose inputs are connected to the selected bit and reference bit lines (Bl, Blref), respectively, where each converter can precharge the associated bit line to a first precharge voltage (Vbias 1) in the precharge phase, a read current generator (GEN) for establishing the data at device output in the following estimation phase, circuits (PCHMTX, PCHREF) for precharging the inputs of differential amplifier to a second precharge voltage (Vbias 2), which is between the first precharge voltage (Vbias 1) and the supply voltage (Vdd), and a circuit (50) in the control block for detecting the end of precharge phase in order to stop the precharge and activate the read current generator (GEN) for the estimation phase. The read current generator (GEN) receives a control signal (MIR) for deactivation in the precharge phase and activation in the estimation phase, where the signal is provided by a control block (5) comprising the circuit (50) for detecting the voltage drop at the input (ER) of converter, and a logic circuit (51). The second precharge voltage (Vbias 2) is about 1.5 V. The device in detailed embodiment also comprises means for equalization of internal nodes controlled by the signal (MIR), and the means are in the form of passgates. Each converter (CIVD, CIVR) comprises a transistor (T1) connected between input and output of converter, and an inverter (I1) connected between the input of converter and the gate of transistor. The circuit (50) comprises two inverters, one dimensioned so to detect the voltage drop before the other associated with the reference bit line. An integrated circuit memory comprises a reading device according to the invention.