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公开(公告)号:JP2000058756A
公开(公告)日:2000-02-25
申请号:JP12036299
申请日:1999-04-27
Applicant: ST MICROELECTRONICS SRL
Inventor: MILANESI ANDREA , CHICCA STEFANIA , MORELLI MARCO , POLETTO VANNI
IPC: H01L27/04 , H01L21/822 , H03K17/082
Abstract: PROBLEM TO BE SOLVED: To totally remove a reverse-direction current and to minimize the bias current of a protection circuit by using an additional MOS transistor to switch off a second DMOS protection transistor during the period under 'below ground' condition. SOLUTION: A 'below ground' voltage condition, for example, of the integrated substrate of a device forming a diagnostic interface is detected by a comparator, which switches off a current generator I through a logic AND gate. At the same time, a current generator I2 which keeps an MOS transistor M at a high impedance state during the normal operation of a control unit is also switched off while a current generator I1 is switched on through an impedance to immediately decide switching-on of the MOS transistor M. Thus, a reverse- direction current flowing through a diagnostic output line VOUT is totally removed, while a bias current level is minimized.
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公开(公告)号:DE69818425D1
公开(公告)日:2003-10-30
申请号:DE69818425
申请日:1998-04-27
Applicant: ST MICROELECTRONICS SRL
Inventor: MILANESI ANDREA , CHICCA STEFANIA , MORELLI MARCO , POLETTO VANNI
IPC: H01L27/04 , H01L21/822 , H03K17/082 , H02H1/00 , G01R31/00
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公开(公告)号:DE69905238T2
公开(公告)日:2003-06-26
申请号:DE69905238
申请日:1999-05-13
Applicant: ST MICROELECTRONICS SRL , MAGNETI MARELLI POWERTRAIN SPA
Inventor: MILANESI ANDREA , CHICCA STEFANIA , POLETTO VANNI , GIORGETTA VALERIO , SGATTI STEFANO , VIGNA SERGIO
IPC: G01R31/02
Abstract: A system is described for the diagnosis of a driver (D) of the type adapted to detect one or more circuit anomalies which can occur in the said driver, including: voltage comparator circuits (10, 20) adapted to generate diagnostic logic signals (F1, F2, F3) each indicative of the existence of a corresponding type of anomaly; and a coding circuit (M, SM) adapted to receive these diagnostic signals (F1, F2, F3) and to output information relating to an overall operating state of the circuit. The coding circuit (M, SM) includes a first portion adapted to provide at its output first logic signals (SHB, SHG, OL) indicative of the last anomaly occurred since a system reset operation, and a second portion for coding such first logic signals (SHB, SHG, OL). The second portion includes a sequential logic network (SM) adapted to: receive the first logic input signals (SHB, SHG, OL) and at least one second logic signal (IN) indicative of the current operating phase of the driver (D); and achieve, as a function of the said first and second logic signals (SHB, SHG, OL; IN) a stable internal state such as to determine at the output information in the form of an N bit coded word representative of an occurred anomaly, of a condition of absence of anomaly in the current operating phase, or of a condition of absence of anomaly in any operating phase.
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公开(公告)号:ES2156269T3
公开(公告)日:2001-06-16
申请号:ES96830472
申请日:1996-09-17
Applicant: ST MICROELECTRONICS SRL , MAGNETI MARELLI SPA
Inventor: CRESPI ANGELO , CHICCA STEFANIA , MASTELLA PAOLO , POLETTO VANNI
Abstract: A circuit for diagnosing the state of a load (LD) comprises a DMOS transistor (DMOS1) interposed between a terminal (OUT) of the load (LD) and voltage comparator circuits (CDT) in order to limit the maximum voltage input to the comparators (CDT) to reduce the circuit area occupied by the comparators (CDT) and consequently the cost of the diagnosis circuit.
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公开(公告)号:ES2191407T3
公开(公告)日:2003-09-01
申请号:ES99830294
申请日:1999-05-13
Applicant: ST MICROELECTRONICS SRL , MAGNETI MARELLI POWERTRAIN SPA
Inventor: MILANESI ANDREA , CHICCA STEFANIA , POLETTO VANNI , GIORGETTA VALERIO , SGATTI STEFANO , VIGNA SERGIO
IPC: G01R31/02
Abstract: A system is described for the diagnosis of a driver (D) of the type adapted to detect one or more circuit anomalies which can occur in the said driver, including: voltage comparator circuits (10, 20) adapted to generate diagnostic logic signals (F1, F2, F3) each indicative of the existence of a corresponding type of anomaly; and a coding circuit (M, SM) adapted to receive these diagnostic signals (F1, F2, F3) and to output information relating to an overall operating state of the circuit. The coding circuit (M, SM) includes a first portion adapted to provide at its output first logic signals (SHB, SHG, OL) indicative of the last anomaly occurred since a system reset operation, and a second portion for coding such first logic signals (SHB, SHG, OL). The second portion includes a sequential logic network (SM) adapted to: receive the first logic input signals (SHB, SHG, OL) and at least one second logic signal (IN) indicative of the current operating phase of the driver (D); and achieve, as a function of the said first and second logic signals (SHB, SHG, OL; IN) a stable internal state such as to determine at the output information in the form of an N bit coded word representative of an occurred anomaly, of a condition of absence of anomaly in the current operating phase, or of a condition of absence of anomaly in any operating phase.
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公开(公告)号:DE69905238D1
公开(公告)日:2003-03-13
申请号:DE69905238
申请日:1999-05-13
Applicant: ST MICROELECTRONICS SRL , MAGNETI MARELLI POWERTRAIN SPA
Inventor: MILANESI ANDREA , CHICCA STEFANIA , POLETTO VANNI , GIORGETTA VALERIO , SGATTI STEFANO , VIGNA SERGIO
IPC: G01R31/02
Abstract: A system is described for the diagnosis of a driver (D) of the type adapted to detect one or more circuit anomalies which can occur in the said driver, including: voltage comparator circuits (10, 20) adapted to generate diagnostic logic signals (F1, F2, F3) each indicative of the existence of a corresponding type of anomaly; and a coding circuit (M, SM) adapted to receive these diagnostic signals (F1, F2, F3) and to output information relating to an overall operating state of the circuit. The coding circuit (M, SM) includes a first portion adapted to provide at its output first logic signals (SHB, SHG, OL) indicative of the last anomaly occurred since a system reset operation, and a second portion for coding such first logic signals (SHB, SHG, OL). The second portion includes a sequential logic network (SM) adapted to: receive the first logic input signals (SHB, SHG, OL) and at least one second logic signal (IN) indicative of the current operating phase of the driver (D); and achieve, as a function of the said first and second logic signals (SHB, SHG, OL; IN) a stable internal state such as to determine at the output information in the form of an N bit coded word representative of an occurred anomaly, of a condition of absence of anomaly in the current operating phase, or of a condition of absence of anomaly in any operating phase.
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公开(公告)号:DE69611826T2
公开(公告)日:2001-06-07
申请号:DE69611826
申请日:1996-09-17
Applicant: ST MICROELECTRONICS SRL , MAGNETI MARELLI SPA
Inventor: CRESPI ANGELO , CHICCA STEFANIA , MASTELLA PAOLO , POLETTO VANNI
Abstract: A circuit for diagnosing the state of a load (LD) comprises a DMOS transistor (DMOS1) interposed between a terminal (OUT) of the load (LD) and voltage comparator circuits (CDT) in order to limit the maximum voltage input to the comparators (CDT) to reduce the circuit area occupied by the comparators (CDT) and consequently the cost of the diagnosis circuit.
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公开(公告)号:DE69611826D1
公开(公告)日:2001-03-29
申请号:DE69611826
申请日:1996-09-17
Applicant: ST MICROELECTRONICS SRL , MAGNETI MARELLI SPA
Inventor: CRESPI ANGELO , CHICCA STEFANIA , MASTELLA PAOLO , POLETTO VANNI
Abstract: A circuit for diagnosing the state of a load (LD) comprises a DMOS transistor (DMOS1) interposed between a terminal (OUT) of the load (LD) and voltage comparator circuits (CDT) in order to limit the maximum voltage input to the comparators (CDT) to reduce the circuit area occupied by the comparators (CDT) and consequently the cost of the diagnosis circuit.
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