公开(公告)号：DE60118697D1

公开(公告)日：2006-05-24

申请号：DE60118697

申请日：2001-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  CONCEPITO ORESTE

IPC: G05F3/30

Abstract: Bandgap type reference voltage source using an operational transimpedance amplifier (31). The bandgap stage is formed by a first and a second bandgap branch (2, 3) parallel-connected; the first bandgap branch (2) comprises a first diode (6) and a transistor (5), series-connected and forming a first output node (10); the second bandgap branch (3) comprises a second diode (9) and a second transistor (7) series-connected and forming a second output node (11). The operational amplifier (31) has inputs (31a, 31b) connected to the output nodes (10, 11) of the bandgap stage (18). An amplifier current detecting stage (40) is connected to the outputs (37a, 38a) of the operational amplifier (31) and supplies a current (IRES) related to the current drawn by the operational amplifier (31). A diode current detecting stage (41) is connected to the output (40c) of the amplifier current detecting stage (40) and to an output (38a) of the operational amplifier (31) and supplies a current (ID) related to the current (I) flowing in the first diode (6). An output stage (33) transforms this current into a stabilized voltage.

公开(公告)号：DE60123925D1

公开(公告)日：2006-11-30

申请号：DE60123925

申请日：2001-04-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  CONCEPITO ORESTE

IPC: G05F3/22 ,  G05F3/24

Abstract: The present invention relates to a current reference circuit for low supply voltages comprising a current source (I), connected at a side to a supply voltage (Vcc) and to the other side to a series (21) composed by a resistance (R2) and diode (D1), said diode (D1) having the cathode electrode connected to the ground and the anode electrode connected with said resistance (R2), characterized in that to comprise also a transistor (M1) and an operational amplifier (OP), said transistor (M1) having the gate electrode connected to the output of said operational amplifier (OP), said transistor (M1) having the source electrode connected to the ground, said transistor (M1) having the drain electrode connected to the positive electrode of said operational amplifier (OP), with said current source (I) and with said series (21), said operational amplifier (OP) having the negative electrode connected to a band gap reference voltage (VBG).

公开(公告)号：ITRM20010282D0

公开(公告)日：2001-05-24

申请号：ITRM20010282

申请日：2001-05-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  CONCEPITO ORESTE

IPC: G11C16/24 ,  G11C16/28

Abstract: A reading circuit for a memory includes a current detector for each bit line of the memory, a reference voltage generator, and a comparator that compares the reference voltage with the voltage of a reading terminal of the current detector. Each current detector includes a first transistor whose gate is selectively connected to the reading terminal, and whose drain-source path is in series with a respective bit line. An input of a first inverter stage is connected to the source of the first transistor, and an output thereof is connected to the gate of the first transistor. The circuit has a very short reading time based upon each of the current detectors including a first resistor between the source of the first transistor and the bit line, along with second and third transistors having their drain-source paths connected in series with the respective bit line, and along with second and third inverters connected to the respective bit line. First and second resistive elements are also connected between the first and second transistors and the respective bit line.

公开(公告)号：ITRM20010282A1

公开(公告)日：2002-11-25

申请号：ITRM20010282

申请日：2001-05-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  CONCEPITO ORESTE

IPC: G11C16/24 ,  G11C16/28

Abstract: A reading circuit for a memory includes a current detector for each bit line of the memory, a reference voltage generator, and a comparator that compares the reference voltage with the voltage of a reading terminal of the current detector. Each current detector includes a first transistor whose gate is selectively connected to the reading terminal, and whose drain-source path is in series with a respective bit line. An input of a first inverter stage is connected to the source of the first transistor, and an output thereof is connected to the gate of the first transistor. The circuit has a very short reading time based upon each of the current detectors including a first resistor between the source of the first transistor and the bit line, along with second and third transistors having their drain-source paths connected in series with the respective bit line, and along with second and third inverters connected to the respective bit line. First and second resistive elements are also connected between the first and second transistors and the respective bit line.