公开(公告)号：IT1319597B1

公开(公告)日：2003-10-20

申请号：ITMI20002763

申请日：2000-12-20

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  LA ROCCA ROSANNA MARIA ,  MATRANGA GIOVANNI

IPC: G11C16/28

Abstract: A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.

公开(公告)号：ITMI20002763A1

公开(公告)日：2002-06-20

申请号：ITMI20002763

申请日：2000-12-20

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  LA ROCCA ROSANNA MARIA ,  MATRANGA GIOVANNI

IPC: G11C16/28

Abstract: A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.