公开(公告)号：DE602005009801D1

公开(公告)日：2008-10-30

申请号：DE602005009801

申请日：2005-04-11

Applicant: ST MICROELECTRONICS SRL

Inventor： LERTORA FRANCESCO ,  BORGATTI MICHELE

IPC: G06F15/78 ,  G06F17/50 ,  H04L12/56

Abstract: A system-on-chip arrangement includes, in possible combination with a processor (100): - a plurality of reconfigurable gate array devices (1001, 1002, 1003), and - a configurable Network-on-Chip (1004) connecting the gate-array devices (1001, 1002, 1003) to render the arrangement scalable. The arrangement lends itself to be operated by: - mapping in one device of the plurality (1001, 1002, 1003) a set of processing modules, and - configuring another device of the plurality (1001, 1002, 1003) as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality (1001, 1002, 1003). The arrangement is thus adapted e.g. to handle different computational granularity levels.