公开(公告)号：JPH07141894A

公开(公告)日：1995-06-02

申请号：JP13909694

申请日：1994-06-21

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G06F12/16 ,  G11C5/14 ,  G11C16/06 ,  G11C17/00

Abstract: PURPOSE: To prevent the failure of a memory by providing a control means to disable a comparator operation and turn on a switch when a first and a second power supply voltages are different from a prescribed threshold value by a certain value. CONSTITUTION: A threshold voltage for a PMOS transistor is expressed as VTH, a programming voltage as VPP, and a reference voltage as VREF. When VCC

公开(公告)号：JPH07141320A

公开(公告)日：1995-06-02

申请号：JP13909794

申请日：1994-06-21

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G11C17/00 ,  G06F15/78 ,  G11C16/02 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/48 ,  G11C29/50 ,  G11C16/06

Abstract: PURPOSE: To directly read the current of the integrated memory cells of a microcontroller by supplying a low voltage to the programming voltage supply line of a memory array, performing the write operation of the prescribed cell of the memory array and measuring the current flowing to the cell. CONSTITUTION: A node 19 is connected through a voltage supply line 16 and a switch 17 composed of an MOS transistor to a pin 18 supplied with a programming voltage Vpp. A programmable voltage source 30 and an ammeter or other current measuring element 31 are present at the outside of this microcontroller 1 and connected to the pin 18. By writing the read bit of a data cell or a reference cell in the cells 23 and 27 of a control register, selecting a prescribed pair of the cells by a word line and a data input bus, applying 1V to a programming pin 18 and issuing a write instruction (thus generating a high logic level in a write enable line W-EN and turning ON the switch 17), the cell is measured.

公开(公告)号：ITVA20020066A1

公开(公告)日：2004-06-05

申请号：ITVA20020066

申请日：2002-12-04

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G06F20060101 ,  G06F13/24 ,  G06F13/26

公开(公告)号：BRPI0105641B1

公开(公告)日：2016-03-01

申请号：BR0105641

申请日：2001-10-15

Applicant: MAGNETI MARELLI POWERTRAIN SPA ,  ST MICROELECTRONICS SRL

Inventor： FERRARI ALBERTO ,  PEPI ALESSANDRO ,  MARCECA PAOLO ,  PEZZINI SAVERIO

IPC: F02D41/26 ,  G05B19/042 ,  G05F1/00 ,  G11C16/10

Abstract: "dispositivo de controle para um motor de veículo". dispositivo que compreende uma unidade de memória (130) para armazenagem de parâmetros de configuração de motores, unidade de processamento (120) para o envio de sinais de controle para o motor conforme os parâmetros de configuração e uma unidade de entrada e saída (140) - (150) conectável a um computador externo (155), a fim de modificar os parâmetros de configuração; o dispositivo de controle inclui uma primeira parte (130a) e uma segunda parte (130b) da unidade de memória, com cada parte sendo útil alternadamente em estado ativo para armazenagem de uma versão atual dos parâmetros de configuração ou em estado inativo para a escrita de uma nova versão dos parâmetros de configuração, a unidade de processamento acessando a parte que se encontra no estado ativo, para leitura, e a unidade de entrada e saída acessando a parte que se encontra no estado inativo, para escrita, e meios (210) - (240) para comutar seletivamente uma das partes para o estado ativo e a outra parte para o estado inativo.

公开(公告)号：DE69326329T2

公开(公告)日：2000-04-13

申请号：DE69326329

申请日：1993-06-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G11C17/00 ,  G06F15/78 ,  G11C16/02 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/48 ,  G11C29/50 ,  G11C16/06

Abstract: A method of directly reading the current of cells (7, 8) of a memory (3) forming part of a microcontroller (1, 1') by performing a write operation of the cells and using the existing cell programming logic. For this purpose, the programming voltage supply line (16) is supplied with a low voltage (e.g. 1 V); the word line of the cell for reading is enabled; and a write instruction of a data item presenting a predetermined logic level (e.g. zero) is performed at the bit corresponding to the cell for reading. By providing an additional pass transistor (25) connected to each reference bit line (RBL) and an additional reference cell enabling line (REF-EN), the reference cells (8) may also be read directly.

公开(公告)号：DE69314013T2

公开(公告)日：1998-02-19

申请号：DE69314013

申请日：1993-06-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G11C5/14 ,  G06F12/16 ,  G11C16/06 ,  G11C17/00

Abstract: A protection circuit (1) comprising a first and second supply line (8, 9) at a first and second supply voltage (VCC, VPP) respectively; a reference voltage source (3); a comparator (2) connected to the first supply line (8) and the source; and a switch (30) controlled by the comparator via a control terminal and located between the second supply line (9) and the output (31) of the circuit (1). To reduce static consumption of the comparator (2) under normal operating conditions, the circuit (1) comprises enabling control elements (4-6, 29) connected to the two supply lines (8, 9) and to the comparator (2) for disabling the comparator and turning on the switch (30) when the two supply voltages differ by a value below a predetermined threshold, but are greater than a reference value.

公开(公告)号：ES2260102T3

公开(公告)日：2006-11-01

申请号：ES01101520

申请日：2001-01-24

Applicant: ST MICROELECTRONICS SRL ,  MAGNETI MARELLI POWERTRAIN SPA

Inventor： PEPI ALESSANDRO ,  PEZZINI SAVERIO ,  MARCECA PAOLO ,  FERRARI ALBERTO

IPC: F02D41/24 ,  F02D41/26 ,  G05B19/042 ,  G11C16/10

Abstract: Un dispositivo (110) de control para un motor (105) de un vehículo, que comprende una unidad (130) de memoria para almacenar parámetros de configuración del motor, una unidad (120) de procesamiento para enviar señales de control al motor de acuerdo con los parámetros de configuración, y una unidad (140-150) de entrada/ salida conectable a un ordenador externo (155) con el fin de modificar los parámetros de configuración, incluyendo el dispositivo (110) de control una primera porción (130a) y una segunda porción (130b) de la unidad de memoria, siendo cada porción utilizable alternativamente en estado activo para almacenar una versión actual de los parámetros de configuración, o en estado inactivo para la escritura de una nueva versión de los parámetros de configuración, accediendo la unidad de procesamiento a la porción que está en estado activo, para lectura, y accediendo la unidad de entrada/ salida a la porción que está en estado inactivo, para escritura, y medios (210-240) para conmutarselectivamente una de las porciones al estado activo y la otra de las porciones al estado inactivo; caracterizado porque la primera porción y la segunda porción consisten, respectivamente, en un primer banco (130a) y en un segundo banco (130b) de una sola memoria (130) E2PROM flash de lectura y escritura simultáneas, y porque dicha unidad (130) de memoria está predispuesta para el suministro de una señal de terminación de una operación de escritura a la unidad (140 - 150) de entrada/ salida por una línea dedicada, y la unidad (140-150) de entrada/ salida está predispuesta para aceptar un comando de escritura procedente del ordenador externo (155) solamente si se ha activado la señal de terminación.

公开(公告)号：DE60205106T2

公开(公告)日：2006-05-24

申请号：DE60205106

申请日：2002-08-07

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G06F13/38

Abstract: A serial interface for communicating with peripherals has circuit means for generating pointers to the single bits of words addressed in the memory sections, circuit means of serial transfer of data from or to at least a peripheral connectable to the interface, coupled to the memory and executing the configuration command pointed in the memory section for storing commands, and a relative control register coupled to the memory and to the circuit means of serial transfer, controlling the transfer of data to be transmitted or received. The interface does not require that an external controller provide configuration commands for each datum to be transmitted or received because the memory sections for storing data are divided in distinct memory spaces and each memory space is destined to store data pertaining to a respective peripheral connected to the interface, the memory section destined to store commands contains all the configuration commands of the interface for communicating with peripherals connected to it and the interface comprises an additional circuit for generating addresses to the memory section storing the configuration commands. This circuit is input with addresses provided on the external address bus and generates, in function of them, corresponding addresses at which the appropriate configuration commands to be executed are stored. A method of managing a serial peripheral interface is also disclosed.

公开(公告)号：ITVA20020066D0

公开(公告)日：2002-12-04

申请号：ITVA20020066

申请日：2002-12-04

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G06F13/24 ,  G06F13/26

Abstract: An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt control circuit associated with the microprocessor. The auxiliary control circuit may include an auxiliary register coupled to the priority interrupt register for storing a copy of the interrupt requests. It may further include an encoder coupled to the auxiliary register and the microprocessor for generating a bit string identifying an active bit stored in the auxiliary register corresponding to a highest priority interrupt request to be processed, and for providing the bit string to the microprocessor.

公开(公告)号：BR0105641A

公开(公告)日：2002-05-28

申请号：BR0105641

申请日：2001-10-15

Applicant: ST MICROELECTRONICS SRL ,  MAGNETI MARELLI POWERTRAIN SPA

Inventor： PEPI ALESSANDRO ,  PEZZINI SAVERIO ,  MARCECA PAOLO ,  FERRARI ALBERTO

IPC: G05F1/00