公开(公告)号：JPH11251452A

公开(公告)日：1999-09-17

申请号：JP37123998

申请日：1998-12-25

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  PIZZUTO OLIVIER

IPC: H01L21/28 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115

Abstract: PROBLEM TO BE SOLVED: To reduce the contact resistance and improve response speed by providing a high voltage transistor with a lightly doped drain region, and by providing a low voltage transistor with the lightly doped region and a more doped region adjacent to a gate region in the drain region and source region, respectively. SOLUTION: A drain region 6 of a high voltage transistor 2 is formed by implanting an N impurity to a substrate 1, and a source region 7 is formed by implanting an N impurity to the substrate 1. In the drain region 8 and the source region 9 of a low voltage transistor 3, a first part 10 is formed by implanting the N impurity to the substrate 1, and a second part 11 is formed by implanting the N impurity to the substrate 1, so as not to have the second part 11 aligned with a gate region 5. The gate region 5 is composed of a polysilicon layer insulated from the substrate 1 by another oxide layer, and a silicon oxide layer 23 that also covers the second part 11 is formed thereon. Then, in the drain region 6 and the source region 7 of the high voltage transistor, a contact region 4' which is doped higher with the impurity than the drain region 6, and the source region 7 is provided.