公开(公告)号：JP2000056946A

公开(公告)日：2000-02-25

申请号：JP12688799

申请日：1999-05-07

Applicant: ST MICROELECTRONICS SRL

Inventor： SAVO PIERANDREA ,  ZANGRANDI LUIGI ,  MARCHESES STEFANO

IPC: G06F7/505 ,  G06F7/00 ,  G06F7/50 ,  G06F7/509

Abstract: PROBLEM TO BE SOLVED: To provide a digital accumulator operatable at a high speed in a wide dynamic range. SOLUTION: A digital accumulator 10 contains a first adder stage 15 where an input addend is added to the least significant value of the output of the accumulator at a previous clock cycle. The accumulator contains at least one second stage and it has an incremental/decremental unit means 18 for executing an incremental, decremental or identification operation on the most significant output of the accumulator. The incremental/decremental unit means contains a logic means for triggering the incremental, decremental or identification operation on the most significant output of the accumulator based on decision by a result obtained at the previous clock cycle.

公开(公告)号：DE69817153D1

公开(公告)日：2003-09-18

申请号：DE69817153

申请日：1998-05-08

Applicant: ST MICROELECTRONICS SRL

Inventor： SAVO PIERANDREA ,  ZANGRANDI LUIGI ,  MARCHESE STEFANO

IPC: G06F7/505 ,  G06F7/00 ,  G06F7/50 ,  G06F7/509