公开(公告)号：JPH11232878A

公开(公告)日：1999-08-27

申请号：JP33991098

申请日：1998-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOOHER MICHAEL ,  TONELLO STEFANO

IPC: G11C11/412

Abstract: PROBLEM TO BE SOLVED: To obtain a RAM memory cell with which power consumption is reduced and which is useful for memory structure having very long work length. SOLUTION: This RAM memory cell comprises first and second cross- connected CMOS inverters 12, 13 comprising respectively PMOS pull-up transistors M3, M4 and NMOS pull-down transistors M1, M2, and first and second success transistors M5, M6 connecting respectively the second inverter 13 and the first inverter 12 to corresponding bit lines. And source temporal of the pull-down transistors M1, M2 are connected to pre-charge lines PL extending in parallel to respective word lines. Further, the first and the second access transistors M5, M6 are PMOS transistors whose gate terminals are connected to word lines WL.

公开(公告)号：ITMI981768D0

公开(公告)日：1998-07-30

申请号：ITMI981768

申请日：1998-07-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOOHER MICHAEL

IPC: G11C7/22

Abstract: The invention relates to a pulse generator circuitry for timing a low-power memory device of a type associated to a memory matrix, including a plurality of word lines driven by a row decoder, and a plurality of bit lines sensed by sense amplifiers. The matrix includes at least a dummy row and at least one dummy column. A delay chain of the pulse generator is formed by the dummy datapath of the memory matrix. The dummy datapath being defined by at least on dummy row and at least one dummy column. The datapath operates prior to the operation of the normal row and column path of the matrix.In another embodiment disclosed, the row decoder comprises a dummy row enable portion at the intersection between the dummy row and the dummy column. The delay chain includes at least the dummy row enable portion, the dummy row and the dummy column.

公开(公告)号：DE69727581D1

公开(公告)日：2004-03-18

申请号：DE69727581

申请日：1997-11-28

Applicant: ST MICROELECTRONICS SRL

Inventor： TOOHER MICHAEL ,  TONELLO STEFANO

IPC: G11C11/412 ,  G11C11/40

Abstract: The invention relates to a RAM memory cell (10) for a memory matrix comprising a plurality of word-lines (WL) and bit-lines (BL), said cell (10) including a first and a second cross-coupled CMOS inverters (12, 13), each including a PMOS pull-up transistor (M3, M4) and an NMOS pull-down transistor (M1, M2), and first and second access transistors (M5, M6) connecting the second (13) and the first inverter (12) to a corresponding bit line respectively, characterized in that the source terminals of the pull-down transistors (M1, M2) are connected to a precharge line (PL) running parallel to each word line. Moreover, the first and second access transistors (M5. M6) are PMOS transistors having their gate terminals connected to the word line (WL).

公开(公告)号：DE69630773D1

公开(公告)日：2003-12-24

申请号：DE69630773

申请日：1996-04-11

Applicant: ST MICROELECTRONICS SRL

Inventor： TOOHER MICHAEL

IPC: G11C8/14 ,  G11C8/00

Abstract: The invention relates to a memory comprising memory cells (10) arranged in continuous rows which are divided in at least two subrows separately selectable by a row decoder (12) through respective word selection metallizations. Each word selection metallization (WL) extends over the row containing the corresponding subrow and the subrows of each row are interlaced.

公开(公告)号：IT1301879B1

公开(公告)日：2000-07-07

申请号：ITMI981768

申请日：1998-07-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOOHER MICHAEL

IPC: G11C7/22

Abstract: The invention relates to a pulse generator circuitry for timing a low-power memory device of a type associated to a memory matrix, including a plurality of word lines driven by a row decoder, and a plurality of bit lines sensed by sense amplifiers. The matrix includes at least a dummy row and at least one dummy column. A delay chain of the pulse generator is formed by the dummy datapath of the memory matrix. The dummy datapath being defined by at least on dummy row and at least one dummy column. The datapath operates prior to the operation of the normal row and column path of the matrix.In another embodiment disclosed, the row decoder comprises a dummy row enable portion at the intersection between the dummy row and the dummy column. The delay chain includes at least the dummy row enable portion, the dummy row and the dummy column.

公开(公告)号：ITMI981768A1

公开(公告)日：2000-01-30

申请号：ITMI981768

申请日：1998-07-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOOHER MICHAEL

IPC: G11C7/22

Abstract: The invention relates to a pulse generator circuitry for timing a low-power memory device of a type associated to a memory matrix, including a plurality of word lines driven by a row decoder, and a plurality of bit lines sensed by sense amplifiers. The matrix includes at least a dummy row and at least one dummy column. A delay chain of the pulse generator is formed by the dummy datapath of the memory matrix. The dummy datapath being defined by at least on dummy row and at least one dummy column. The datapath operates prior to the operation of the normal row and column path of the matrix.In another embodiment disclosed, the row decoder comprises a dummy row enable portion at the intersection between the dummy row and the dummy column. The delay chain includes at least the dummy row enable portion, the dummy row and the dummy column.