公开(公告)号：DE602005025962D1

公开(公告)日：2011-03-03

申请号：DE602005025962

申请日：2005-06-24

Applicant: ST MICROELECTRONICS SRL ,  ST MICROELECTRONICS INC

Inventor： PASOLINI FABIO ,  TRONCONI MICHELE ,  LIN WEN ,  RAASCH WILLIAM

IPC: G01P15/00 ,  G01P15/18 ,  G11B19/04

公开(公告)号：JP2003186818A

公开(公告)日：2003-07-04

申请号：JP2002252295

申请日：2002-08-30

Applicant: ST MICROELECTRONICS INC

Inventor： LIN WEN

IPC: G06F13/10 ,  G06F3/06 ,  G06F13/00 ,  G06F13/28

Abstract: PROBLEM TO BE SOLVED: To provide a system architecture which improves the efficiency of data processing capability in an integrated system. SOLUTION: A computer system has a processor with a data/control bus interface. A data/control bus implements one or more device communication channels. A data memory is coupled to the processor and a mass storage device having an interface for communicating mass storage transaction, is provided. A controller having a memory interface is coupled to the data memory and a mass storage interface coupled to the mass storage device's interface and operable to conduct mass storage transactions between the data memory and the mass storage device. COPYRIGHT: (C)2003,JPO