公开(公告)号：US20230005540A1

公开(公告)日：2023-01-05

申请号：US17930250

申请日：2022-09-07

Applicant: ST Microelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C14/00

Abstract: An embodiment integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node.

公开(公告)号：US20230301076A1

公开(公告)日：2023-09-21

申请号：US18321487

申请日：2023-05-22

Applicant: ST Microelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H10B41/00 ,  H01L29/423 ,  G11C7/18 ,  H01L29/66 ,  G11C16/04 ,  H01L21/28 ,  G11C16/08 ,  G11C16/24 ,  H10B41/35

CPC classification number: H10B41/00 ,  G11C7/18 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66825 ,  H10B41/35 ,  H01L29/7881

Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.