WAFER LEVEL GATE MODULATION ENHANCED DETECTORS
    1.
    发明申请
    WAFER LEVEL GATE MODULATION ENHANCED DETECTORS 审中-公开
    晶片级门调制增强型探测器

    公开(公告)号:WO2017189124A1

    公开(公告)日:2017-11-02

    申请号:PCT/US2017/023424

    申请日:2017-03-21

    Applicant: STC. UNM

    Abstract: A detector or sensor including a transistor having a sensor element that generates a current when exposed to a stimulus such as light or a chemical, in one implementation, the sensor element is positioned between a transistor gate and a transistor channel. When the sensor element is not being exposed to the stimulus, the transistor outputs a first voltage on a transistor drain contact when the transistor Inverts. When the sensor element is being exposed to the stimulus, the transistor outputs a second voltage on the transistor drain contact when the transistor inverts, where the second voltage is higher than the first voltage.

    Abstract translation: 在一种实施方式中,包括具有传感器元件的晶体管的检测器或传感器在一种实施方式中在传感器元件暴露于诸如光或化学物质的刺激时产生电流,传感器元件位于晶体管栅极和 晶体管通道。 当传感器元件未暴露于刺激时,当晶体管Inverts时,晶体管在晶体管漏极触点上输出第一电压。 当传感器元件暴露于刺激时,当晶体管反相时,晶体管在晶体管漏极触点上输出第二电压,其中第二电压高于第一电压。

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