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    Decision feedback equalization scheme with minimum correction delay
    1.
    发明授权
    Decision feedback equalization scheme with minimum correction delay 有权
    具有最小校正延迟的判决反馈均衡方案

    公开(公告)号：US08699559B2

    公开(公告)日：2014-04-15

    申请号：US13772872

    申请日：2013-02-21

    Applicant: STMicroelectronics S.R.L.

    Inventor： Simone Erba ,  Massimo Pozzoni

    IPC: H04B1/38

    CPC classification number: H04L25/03885 ,  H04L25/03063 ,  H04L25/0307 ,  H04L2025/03356 ,  H04L2025/03579

    Abstract: A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.

    Abstract translation: 判决反馈均衡器包括校正电路，用于基于至少一个先前位的符号间干扰来校正输入位的采样值，并产生接收位。 校正电路包括第一多路复用器和耦合到其上的第一对锁存器。 第一多路复用器由时钟信号控制，以产生代表第一校正系数的符号的数字电平，以便从用于删除符号间干扰的输入位的采样值中减去。 第一对锁存器作为输入接收接收的位，并且通过时钟信号相位对准时钟，以在时钟信号的相应有效相位期间产生接收位的相应锁存副本。 相应的锁存副本被输入到第一多路复用器。

    FREQUENCY DOUBLER AND RELATED METHOD OF GENERATING AN OSCILLATING VOLTAGE
    4.
    发明申请
    FREQUENCY DOUBLER AND RELATED METHOD OF GENERATING AN OSCILLATING VOLTAGE 有权
    频率二极管及相关方法产生振荡电压

    公开(公告)号：US20140361815A1

    公开(公告)日：2014-12-11

    申请号：US14298559

    申请日：2014-06-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Emanuele Depaoli ,  Giovanni Steffan ,  Massimo Pozzoni ,  Simone Erba ,  Enrico Monaco

    IPC: H03K5/00

    CPC classification number: H03K5/00006 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B25/00 ,  H03B2200/0074

    Abstract: A frequency doubling device suitable to generate an output terminal voltage oscillating at a differential frequency double the frequency of the input differential voltage, includes a first differential pair of P-type transistors and a second differential pair of N-type transistors controlled by the differential input voltage, as well as an LC oscillator including a LC resonant dipole through which the absorbed current is forced by two differential pairs of transistors.

    Abstract translation: 适用于产生以差分频率振荡输入差分电压的频率的输出端子电压的倍频装置包括由差分输入端控制的P型晶体管的第一差分对和N型晶体管的第二差分对， 电压以及包括LC谐振偶极子的LC振荡器，吸收的电流通过两个差分对的晶体管被​​迫使。

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