公开(公告)号：WO2012156034A1

公开(公告)日：2012-11-22

申请号：PCT/EP2012/001928

申请日：2012-05-04

Applicant: STMICROELECTRONICS S.R.L. ,  CREMA, Paolo

Inventor： CREMA, Paolo

IPC: H01L21/48 ,  B41C1/14

CPC classification number: H01L24/43 ,  H01L21/4821 ,  H01L2224/43 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: The present invention relates to a method and an apparatus for manufacturing lead frames. According to the present invention, a coating layer (120) is formed on one or more predefined portions (A, B, C, D, E, F, G, H) of the surface (110s) of the substrate (100) of the lead frame (100) by delimiting the predefined portions (A, B, C, D, E, F, G, H) by means of screen printing. The employment of screen printing allows the obtainment of large amounts of lead frames with excellent electronic and structural properties in a quick and cost-effective way.

Abstract translation: 本发明涉及一种用于制造引线框架的方法和装置。 根据本发明，在基板（100）的表面（110s）的一个或多个预定部分（A，B，C，D，E，F，G，H）上形成涂层（120） 通过丝网印刷限定预定部分（A，B，C，D，E，F，G，H）来引导框架（100）。 丝网印刷的使用允许以快速和成本有效的方式获得具有优异的电子和结构特性的大量引线框架。

公开(公告)号：WO2021240305A1

公开(公告)日：2021-12-02

申请号：PCT/IB2021/054304

申请日：2021-05-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： CREMA, Paolo

IPC: H01L23/00

Abstract: A method comprises molding laser direct structuring material (10), having particles (12) dispersed therein, onto at least one semiconductor die (11), applying laser beam energy to produce structured formations (14) with a part of the particles (12) exposed at the structured formations (14), contacting the structured formations (14) with a solution containing one or more organic compounds, forming a film covering at least partly the structured formations (14) and comprising one or more conductive polymers resulting from a polymerization reaction of the one or more organic compounds, and forming electrically-conductive material (24) onto the film.

公开(公告)号：EP3832702A1

公开(公告)日：2021-06-09

申请号：EP20210552.4

申请日：2020-11-30

Applicant: STMicroelectronics S.r.l.

Inventor： CREMA, Paolo

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/495

Abstract: A method of manufacturing semiconductor devices comprises the steps of:
- providing a leadframe (12) having a die pad area (14), the leadframe (12) comprising an outer layer of a first metal having a first oxidation potential,
- contacting said leadframe (12) with a solution (S) containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential,
- applying radiation energy (LB) to the die pad area (14) of the leadframe (12) contacted with said solution (S) to locally increase the temperature of the leadframe (12), wherein a layer of said second metal is selectively provided at the die pad area (14) of the leadframe (12) by galvanic displacement reaction,
- providing onto said leadframe (12) an enhancing layer by oxidation of said outer layer of the leadframe (12), the enhancing layer countering device package delamination,
- attaching onto said die pad area (14) at least one semiconductor die via soft-solder die attach material, and
- forming a device package by molding package material onto the at least one semiconductor die attached onto said die pad area (14) of the leadframe (12).
(Figure 2)

公开(公告)号：EP4016614A1

公开(公告)日：2022-06-22

申请号：EP21214666.6

申请日：2021-12-15

Applicant: STMicroelectronics S.r.l.

Inventor： CREMA, Paolo

IPC: H01L23/495 ,  H01L21/48

Abstract: In a method of manufacturing a multi-die semiconductor device (10), a metal leadframe is provided which includes a die pad (100) and electrically-conductive leads (102) arranged around the die pad. A first (12) and a second (14) semiconductor dice are arranged onto the die pad. A laser-activatable material is provided onto the dice (12, 14) and the leads (102), and a set of laser-activated lines is patterned which includes a first subset of lines coupling selected bonding pads of the dice (12, 14) to selected leads (102), a second subset of lines coupling selected bonding pads of the dice (12, 14) amongst themselves, and a third subset of lines coupling the lines in the second subset of lines to at least one line in the first subset of lines, and/or to at least one electrically-conductive lead. A first metallic layer is deposited onto the laser-activated lines to provide respective first, second and third subsets of electrically-conductive lines. A second metallic layer is selectively deposited onto the first and second subsets of electrically-conductive lines by means of electroplating to provide respective first (16C', 16C) and second (16B', 16B) subsets of electrically-conductive tracks. The electrically-conductive lines in said third subset of electrically-conductive lines are selectively removed.

公开(公告)号：EP1155168B1

公开(公告)日：2006-07-26

申请号：EP99924090.6

申请日：1999-05-18

Applicant: AEM-Tech Engineers Pte Ltd. ,  STMicroelectronics S.r.l.

Inventor： TOK, Kian You,c/o AEM-Tech Engineers Pte Ltd ,  CREMA, Paolo

IPC: C25D5/02

CPC classification number: C25D5/024 ,  B23K26/361 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Method for selective plating of a metal substrate using laser developed masking layer and apparatus for carrying out the method, wherein the method comprises the steps of applying a thin layer of an epoxyurethane, acrylic or epoxy based plating resist on the metal substrate by electrophoretic coating; curing said plating resist on said substrate; selectively removing said plating resist from said substrate by subjecting said plating resist to a laser beam emitted by a frequency doubled Nd:YAG laser having a wavelength of 532 nm and operated at a repetition rate of about 300 Hz; and scanning said laser beam on said plating resist by means of an optical galvo system according to a pattern along which the metal substrate is to be metal plated, wherein the plating resist is selected so as to be at least substantially transparent to the said laser beam and the metal is selected to absorb at least a substantial part of the energy of said laser beam, whereby a substantial portion of the laser energy is transmitted through said plating resist and absorbed by said metal substrate resulting in said metal substrate being heated at the surface thereof to form a plasma at the interface between the coating resist and the metal substrate, the plasma causing the plating resist thereover to blow off thereby exposing the surface of the metal substrate along said pattern suitable for metal plating; and subjecting said substrate to metal plating at the exposed surface thereof.

公开(公告)号：EP1155168A1

公开(公告)日：2001-11-21

申请号：EP99924090.6

申请日：1999-05-18

Applicant: AEM-Tech Engineers Pte Ltd. ,  STMicroelectronics S.r.l.

Inventor： TOK, Kian You ,  CREMA, Paolo

IPC: C25D5/02

CPC classification number: C25D5/024 ,  B23K26/361 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Method for selective plating of a metal substrate using laser developed masking layer and apparatus for carrying out the method, wherein the method comprises the steps of applying a thin layer of an epoxyurethane, acrylic or epoxy based plating resist on the metal substrate by electrophoretic coating; curing said plating resist on said substrate; selectively removing said plating resist from said substrate by subjecting said plating resist to a laser beam emitted by a frequency doubled Nd:YAG laser having a wavelength of 532 nm and operated at a repetition rate of about 300 Hz; and scanning said laser beam on said plating resist by means of an optical galvo system according to a pattern along which the metal substrate is to be metal plated, wherein the plating resist is selected so as to be at least substantially transparent to the said laser beam and the metal is selected to absorb at least a substantial part of the energy of said laser beam, whereby a substantial portion of the laser energy is transmitted through said plating resist and absorbed by said metal substrate resulting in said metal substrate being heated at the surface thereof to form a plasma at the interface between the coating resist and the metal substrate, the plasma causing the plating resist thereover to blow off thereby exposing the surface of the metal substrate along said pattern suitable for metal plating; and subjecting said substrate to metal plating at the exposed surface thereof.

Abstract translation: 用于使用激光开发掩模层和装置用于执行该方法，worin该方法的金属基底的选择性镀覆方法包括施加的环氧聚氨酯，丙烯酸系或环氧系镀上通过电泳涂装的金属基体抗蚀剂的薄层的工序; 所述固化抗镀层在所述的底物; 选择性地去除由使所述防镀层，以通过频率发射的激光束会聚到所述镀层从所述衬底的抗蚀剂倍频Nd：具有532nm的波长的YAG激光器和在约300赫兹的重复率操作; 和扫描所述关于所述激光束镀敷由光学检流计系统雅丁到沿着该金属基片被金属镀覆的图案的手段抗蚀剂，worin的电镀抗蚀剂被选择，以便至少基本上透明的所述激光束 和金属被选择为吸收至少一部分所述激光束的能量，从而使激光能量的相当大的部分是通过所述反mitted电镀抗蚀剂，并通过在所述金属基材得到的所述金属基材吸收在表面被加热的主要部分 其形成在该涂层和该抗蚀剂的金属基材之间的界面处的等离子体，所述等离子体使所述电镀抗蚀剂有超过吹掉从而暴露沿着适合用于金属镀覆所述图案的金属基材的表面上; 且在露出的表面使所说的基底金属电镀物。

公开(公告)号：EP3285295A1

公开(公告)日：2018-02-21

申请号：EP17162016.4

申请日：2017-03-21

Applicant: STMicroelectronics S.r.l.

Inventor： CREMA, Paolo ,  CASATI, Paolo

IPC: H01L23/495

CPC classification number: H01L23/49582 ,  H01L21/4853 ,  H01L23/4952 ,  H01L23/49548 ,  H01L24/09 ,  H01L24/43 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/08058 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85385 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Semiconductor devices (10) comprising at least one electrically conductive metal element (16) in a nonconductive package material (20) are manufactured by:
- providing a first metal layer (102) having a smooth morphology for covering the aforesaid metal element (16); and
- providing a second metal layer (104) for covering partially the first layer (102), leaving at least one portion of the surface of the first layer (102) exposed, the second layer (104) having a rough morphology.
There may moreover be provided a die pad (14) for mounting a semiconductor die (12) by providing the aforesaid first layer (102) for covering the die pad (14) and attaching a semiconductor die (12) on the die pad (14) in contact with said first layer (102).

Abstract translation: 包括在非导电封装材料（20）中的至少一个导电金属元件（16）的半导体器件（10）通过以下制造：提供具有平滑形态的第一金属层（102）以覆盖上述金属元件（16） ; 和 - 提供用于部分地覆盖第一层（102）的第二金属层（104），使第一层（102）的表面的至少一部分暴露，第二层（104）具有粗糙的形态。 此外可以通过提供用于覆盖管芯焊盘（14）的上述第一层（102）并将半导体管芯（12）附着在管芯焊盘（14）上来提供用于安装半导体管芯（12）的管芯焊盘（14） ）与所述第一层（102）接触。