公开(公告)号：EP1942410B1

公开(公告)日：2016-06-29

申请号：EP07254379.6

申请日：2007-11-06

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M.

IPC: G06F9/30

CPC classification number: G06F9/325 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3887

公开(公告)号：EP1942410A2

公开(公告)日：2008-07-09

申请号：EP07254379.6

申请日：2007-11-06

Applicant: STMicroelectronics, Inc

Inventor： Colavin, Osvaldo M.

IPC: G06F9/30

CPC classification number: G06F9/325 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3887

Abstract: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

Abstract translation: 改进的超标量处理器 处理器包括多个通道，允许并行执行捆绑中的多个指令。 在向量模式中，并行通道可用于执行捆绑的多个实例，表示向量运行中捆绑的多次迭代。 调度逻辑决定了对于每个bundle，是否可以并行执行多个实例。 如果并行执行多个实例，则耦合电路将一个实体的捆绑从一个通道耦合到一个或多个其他通道。 在每个通道中，重新命名寄存器地址，以确保在向量运行中正确执行捆绑。 另外，处理器可以包括与架构寄存器文件分离的寄存器组。 重命名逻辑可以为这个单独的寄存器组生成比用于寻址架构寄存器更长的地址，允许更长的向量和更高效的处理器操作。

公开(公告)号：EP1710693B1

公开(公告)日：2011-08-03

申请号：EP06251747.9

申请日：2006-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M. ,  Rizzo, Davide

IPC: G06F9/38

CPC classification number: G06F9/383

公开(公告)号：EP1624443A2

公开(公告)日：2006-02-08

申请号：EP05254807.0

申请日：2005-08-01

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M.

IPC: G09G5/34

CPC classification number: G09G5/346 ,  G09G5/34 ,  G09G2360/121

Abstract: A method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed linear data buffer is used to store a portion of an entire image. The data buffer is larger than the amount of data displayed at one time. A user enters scrolling commands and the display scrolls around the data initially in the buffer. new data is loaded into the buffer as the displayed data approaches the edge of the buffered data.

Abstract translation: 一种用于缓冲的2维图形图像数据的方法和装置将被供应到滚动显示控制器。 二维的，圆形寻址线性数据缓冲器用来存储整个图像的一部分。 数据缓冲器比一次显示的数据量更大。 用户输入在缓冲滚动周围的数据的命令和显示滚动INITIALLY。 新的数据被装载到缓冲液作为所显示的数据接近缓冲的数据的边缘。

公开(公告)号：EP1710693A3

公开(公告)日：2007-11-14

申请号：EP06251747.9

申请日：2006-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M. ,  Rizzo, Davide

IPC: G06F9/38

CPC classification number: G06F9/383

Abstract: A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use in the immediate future. Data is retrieved for the prefetch thread and stored in a memory, such as data fetched from an external memory and stored in a buffer. A prefetch controller determines whether the memory is full. If the memory is full, a cache controller stalls at least one prefetch thread. The stall may continue until at least some of the data is.transferred from the memory to a cache for use by at least one main computing thread. The stalled prefetch thread or threads are then reactivated.

公开(公告)号：EP1710693A2

公开(公告)日：2006-10-11

申请号：EP06251747.9

申请日：2006-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M. ,  Rizzo, Davide

IPC: G06F9/38

CPC classification number: G06F9/383

Abstract: A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use in the immediate future. Data is retrieved for the prefetch thread and stored in a memory, such as data fetched from an external memory and stored in a buffer. A prefetch controller determines whether the memory is full. If the memory is full, a cache controller stalls at least one prefetch thread. The stall may continue until at least some of the data is.transferred from the memory to a cache for use by at least one main computing thread. The stalled prefetch thread or threads are then reactivated.

Abstract translation: 处理器执行一个或多个预取线程和一个或多个主计算线程。 每个预取线程在主计算线程之前执行指令以检索主计算线程的数据，例如主计算线程在不久的将来可能使用的数据。 针对预取线程检索数据并存储在存储器中，例如从外部存储器读取并存储在缓冲器中的数据。 预取控制器确定存储器是否已满。 如果内存已满，缓存控制器至少停止一个预取线程。 停顿可以继续，直到至少一些数据从存储器传送到高速缓存以供至少一个主计算线程使用。 然后重新激活停滞的预取线程或线程。

公开(公告)号：EP1309171A3

公开(公告)日：2004-10-06

申请号：EP02257331.5

申请日：2002-10-22

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M. ,  Lusinchi, Emmanuel

IPC: H04N1/21 ,  H04N1/00

CPC classification number: G06T3/403 ,  G06T3/4038 ,  H04N5/2624 ,  H04N5/772 ,  H04N5/781 ,  H04N5/907

Abstract: A method for storing a plurality of still images to form a panoramic image. The method comprising the steps of receiving a first image forming a part of a series of images to form a panoramic image and storing the first image in memory. When one or more subsequent images after the first image are received the steps of calculating one or more panoramic parameters between a current image and a previous image stored in memory and storing the current image with the one or more panoramic parameters in memory are performed.

公开(公告)号：EP1624443A3

公开(公告)日：2008-12-17

申请号：EP05254807.0

申请日：2005-08-01

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M.

IPC: G09G5/34

CPC classification number: G09G5/346 ,  G09G5/34 ,  G09G2360/121

Abstract: A method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed linear data buffer is used to store a portion of an entire image. The data buffer is larger than the amount of data displayed at one time. A user enters scrolling commands and the display scrolls around the data initially in the buffer. new data is loaded into the buffer as the displayed data approaches the edge of the buffered data.

公开(公告)号：EP1942410A3

公开(公告)日：2008-09-24

申请号：EP07254379.6

申请日：2007-11-06

Applicant: STMicroelectronics, Inc

Inventor： Colavin, Osvaldo M.

IPC: G06F9/30

CPC classification number: G06F9/325 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3887

Abstract: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

Abstract translation: 改进的超标量处理器。 处理器包含多个通道，允许并行执行一个包中的多个指令。 在矢量模式下，平行通道可用于执行一个束的多个实例，表示矢量运行中束的多次迭代。 调度逻辑确定对于每个包是否可以并行执行多个实例。 如果多个实例可以并行执行，则耦合电路将来自一个通道的束实例耦合到一个或多个其他通道。 在每个通道中，寄存器地址被重新命名以确保向量运行中的bundle正确执行。 另外，处理器可以包括与架构寄存器文件分开的寄存器组。 重命名逻辑可以为这个单独的寄存器组生成地址，这些地址比用于寻址体系结构寄存器的时间长，从而允许更长的向量和更高效的处理器操作

公开(公告)号：EP1309171A2

公开(公告)日：2003-05-07

申请号：EP02257331.5

申请日：2002-10-22

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M. ,  Lusinchi, Emmanuel

IPC: H04N1/21 ,  H04N1/00

CPC classification number: G06T3/403 ,  G06T3/4038 ,  H04N5/2624 ,  H04N5/772 ,  H04N5/781 ,  H04N5/907

Abstract: A method for storing a plurality of still images to form a panoramic image. The method comprising the steps of receiving a first image forming a part of a series of images to form a panoramic image and storing the first image in memory. When one or more subsequent images after the first image are received the steps of calculating one or more panoramic parameters between a current image and a previous image stored in memory and storing the current image with the one or more panoramic parameters in memory are performed.

Abstract translation: 一种用于存储多个静止图像以形成全景图像的方法。 该方法包括以下步骤：接收形成一系列图像的一部分以形成全景图像并将第一图像存储在存储器中的第一图像。 当接收到第一图像之后的一个或多个后续图像时，执行计算当前图像与存储在存储器中的先前图像之间的一个或多个全景参数并将当前图像与一个或多个全景参数存储在存储器中的步骤。