Magnetic random access memory array having bit/word lines for shared write select and read operations
    1.
    发明公开
    Magnetic random access memory array having bit/word lines for shared write select and read operations 有权
    Magnetischer Direktzugriffsspeicherarray mit Bit- / Wortleitungenfürgemeinsame Schreibauswahl- und Leseoperationen

    公开(公告)号:EP1736993A1

    公开(公告)日:2006-12-27

    申请号:EP06252950.8

    申请日:2006-06-07

    CPC classification number: G11C7/18 G11C7/12 G11C11/15 G11C11/16

    Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

    Abstract translation: 随机存取存储器阵列包括排列成行和列的随机存取存储器元件。 每行的元素具有字线和写数字线,并且每列的元素具有位线和写位线。 用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。 用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源极 - 漏极路径和耦合到位线的栅极端子。 第一写入信号被施加到一个字线以对与该一条字线相对应的行进行第一选择电路/晶体管的驱动,并且使得写入电流流过被驱动的第一选择电路/晶体管的第一源极 - 漏极通路,并且 相应的写数字行将数据写入该行中的某些存储器元素。 第二写入信号被施加到一个位线以启动与该一个位线对应的列的第二选择电路/晶体管,并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路,并且 相应的写位线将数据写入该列中的至少一个存储器元件。

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