公开(公告)号：EP1612804A2

公开(公告)日：2006-01-04

申请号：EP05254099.4

申请日：2005-06-29

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe

IPC: G11C11/56 ,  G11C11/16

CPC classification number: G11C11/16 ,  G11C11/5607

Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. These magnetic tunnel junctions are connected to each other in a series resistive circuit. The connected first and second magnetic tunnel junctions are connected to a bit line through an access transistor. A write bit line and a write data line are associated with each of the first and second magnetic tunnel junctions. By application of appropriate currents to these lines, the magnetic vector orientation with each of the first and second magnetic tunnel junctions can be controlled so as to store information within the element in any one of at least three logic states.

Abstract translation: 磁性随机存取存储元件由第一磁性隧道结和第二磁性隧道结形成。 这些磁性隧道结在串联电阻电路中相互连接。 连接的第一和第二磁性隧道结通过存取晶体管连接到位线。 写位线和写数据线与第一和第二磁隧道结中的每一个相关联。 通过向这些线路施加适当的电流，可以控制与第一和第二磁性隧道结中的每一个的磁矢量取向，以便将元件中的信息存储在至少三个逻辑状态中的任何一个中。

公开(公告)号：EP1612804B1

公开(公告)日：2009-08-05

申请号：EP05254099.4

申请日：2005-06-29

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe

IPC: G11C11/56 ,  G11C11/16

CPC classification number: G11C11/16 ,  G11C11/5607

公开(公告)号：EP1736993A1

公开(公告)日：2006-12-27

申请号：EP06252950.8

申请日：2006-06-07

Applicant: STMicroelectronics, Inc.

Inventor： Dray, Cyrille ,  Barasinski, Sebastien ,  Lasseuguette, Jean ,  Frey, Christophe ,  Fournel, Richard

IPC: G11C11/16 ,  G11C7/18 ,  G11C8/14

CPC classification number: G11C7/18 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

Abstract translation: 随机存取存储器阵列包括排列成行和列的随机存取存储器元件。 每行的元素具有字线和写数字线，并且每列的元素具有位线和写位线。 用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。 用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源极 - 漏极路径和耦合到位线的栅极端子。 第一写入信号被施加到一个字线以对与该一条字线相对应的行进行第一选择电路/晶体管的驱动，并且使得写入电流流过被驱动的第一选择电路/晶体管的第一源极 - 漏极通路，并且 相应的写数字行将数据写入该行中的某些存储器元素。 第二写入信号被施加到一个位线以启动与该一个位线对应的列的第二选择电路/晶体管，并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路，并且 相应的写位线将数据写入该列中的至少一个存储器元件。

公开(公告)号：EP1612802A3

公开(公告)日：2006-04-26

申请号：EP05254093.7

申请日：2005-06-29

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe

IPC: G11C11/15 ,  G11C11/41

CPC classification number: G11C14/0081 ,  G11C11/16

Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. A latching circuit includes a false node that is connected to the first magnetic tunnel junction and a true node that is connected to the second magnetic tunnel junction. A pair of complementary bit lines are provided in association with the element. A first access transistor inter-connects a false one of the bit lines to the false node of the latching circuit, while a second access transistor inter-connects a true one of the bit lines to the true node of the latching circuit. The memory element accordingly has an SRAM four transistor (4T) two load (2R) architecture wherein the resistances associated with the two magnetic tunnel junctions provide the two load resistances.

公开(公告)号：EP1612804A3

公开(公告)日：2006-04-26

申请号：EP05254099.4

申请日：2005-06-29

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe

IPC: G11C11/56 ,  G11C11/16

CPC classification number: G11C11/16 ,  G11C11/5607

Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. These magnetic tunnel junctions are connected to each other in a series resistive circuit. The connected first and second magnetic tunnel junctions are connected to a bit line through an access transistor. A write bit line and a write data line are associated with each of the first and second magnetic tunnel junctions. By application of appropriate currents to these lines, the magnetic vector orientation with each of the first and second magnetic tunnel junctions can be controlled so as to store information within the element in any one of at least three logic states.

Abstract translation: 磁性随机存取存储器元件由第一磁性隧道结和第二磁性隧道结构成。 这些磁隧道结在一个串联电阻电路中相互连接。 连接的第一和第二磁隧道结通过存取晶体管连接到位线。 写位线和写数据线与第一和第二磁隧道结中的每一个相关联。 通过向这些线施加适当的电流，可以控制第一和第二磁隧道结中的每一个的磁矢量取向，以便以至少三个逻辑状态中的任何一个存储元件内的信息。

公开(公告)号：EP1612807A2

公开(公告)日：2006-01-04

申请号：EP05254094.5

申请日：2005-06-29

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe

IPC: G11C29/00

CPC classification number: G06F11/1076 ,  G11C7/1006 ,  G11C11/16 ,  G11C16/10 ,  G11C2211/5646 ,  G11C2211/5647

Abstract: A random access memory array includes first random access memory elements arranged in a plurality of rows and columns for storing data words at a multiple memory locations. The memory array further includes second random access memory elements arranged in at least one additional column. Each second random access memory element is associated with a memory location to store a flag value indicative of whether the data word stored at that memory location is a true or complement version. The individual memory elements may comprise magnetic random access memory elements. Alternatively, the individual memory elements may comprise flash memory cells.

Abstract translation: 随机存取存储器阵列包括以多个行和列排列的用于在多个存储器位置存储数据字的第一随机存取存储器元件。 存储器阵列还包括布置在至少一个附加列中的第二随机存取存储器元件。 每个第二随机存取存储器元件与存储器位置相关联，以存储指示存储在该存储器位置的数据字是真还是补补版本的标志值。 各个存储元件可以包括磁性随机存取存储器元件。 或者，各个存储元件可以包括闪存单元。

公开(公告)号：EP1612800A2

公开(公告)日：2006-01-04

申请号：EP05254084.6

申请日：2005-06-29

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe

IPC: G11C11/00

CPC classification number: G11C11/16

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. Each row is divided into a plurality of row groups of elements and each column is divided into a plurality of column groups of elements. The elements in each row group share a common local write digit line and the elements in each column group share a common local write bit line. The array further includes at least one global write digit line coupled to the common local write digit lines of plural row groups, and at least one global write bit line coupled to the common local write bit lines of plural column groups.

Abstract translation: 随机存取存储器阵列包括排列成行和列的随机存取存储器元件。 每行被分成多个行组元素，并且每列被分成多个列组元素。 每个行组中的元素共享一个公共的本地写入数字行，并且每个列组中的元素共享一个公共的本地写入位线。 该阵列还包括耦合到多个行组的公共本地写入数字线的至少一个全局写入数字线以及耦合到多个列组的公共本地写入位线的至少一个全局写入位线。

公开(公告)号：EP1612807A3

公开(公告)日：2008-01-23

申请号：EP05254094.5

申请日：2005-06-29

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe

IPC: G11C29/00 ,  G11C15/00

CPC classification number: G06F11/1076 ,  G11C7/1006 ,  G11C11/16 ,  G11C16/10 ,  G11C2211/5646 ,  G11C2211/5647

Abstract: A random access memory array includes first random access memory elements arranged in a plurality of rows and columns for storing data words at a multiple memory locations. The memory array further includes second random access memory elements arranged in at least one additional column. Each second random access memory element is associated with a memory location to store a flag value indicative of whether the data word stored at that memory location is a true or complement version. The individual memory elements may comprise magnetic random access memory elements. Alternatively, the individual memory elements may comprise flash memory cells.

公开(公告)号：EP1369877A3

公开(公告)日：2007-08-08

申请号：EP03253553.6

申请日：2003-06-05

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe ,  LaLanne, Frederic ,  Lysinger, Mark A.

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.

公开(公告)号：EP1612800A3

公开(公告)日：2006-09-06

申请号：EP05254084.6

申请日：2005-06-29

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe

IPC: G11C11/00

CPC classification number: G11C11/16

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. Each row is divided into a plurality of row groups of elements and each column is divided into a plurality of column groups of elements. The elements in each row group share a common local write digit line and the elements in each column group share a common local write bit line. The array further includes at least one global write digit line coupled to the common local write digit lines of plural row groups, and at least one global write bit line coupled to the common local write bit lines of plural column groups.