Abstract:
An electrical connection structure is provided for protecting a barrier metal layer within a contact opening during the formation of an aluminum interconnection layer overlying a tungsten plugged connection structure. The deposited tungsten plug overlying the barrier metal layer is etched back sufficiently to create a slight recess at the opening. A thin layer of tungsten is then selectively deposited for filling the recess. This layer acts as an etch stop during aluminum interconnection layer formation and protects the underlying barrier metal layer.
Abstract:
A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A transistor encapsulated in a dielectric is formed over a substrate. First source and drain regions are formed in the substrate adjacent the transistor. Metal raised second source and drain regions are formed which overly exposed portions of the first substrate source and drain regions adjacent the transistor. The raised second source and drain regions are formed such that an upper surface of the raised second source and drain regions are substantially planar with an upper surface of the transistor. The dielectric encapsulating the transistor electrically isolates the transistor from the raised second source and drain regions.
Abstract:
A method of forming interconnects in an integrated circuit, comprising: forming a dielectric layer over a substrate; forming a groove for an interconnect in the dielectric layer; forming an aluminium seed layer over the upper surface of the dielectric layer, over sidewalls of the groove, and over a bottom of the groove to a thickness of approximately 200 Å; zincating the substrate to form a zinc coating on the aluminium seed layer; plating the substrate with silver to form a conformal silver layer on an upper surface of the dielectric layer and on sidewalls of the groove, filling an unfilled portion of the groove; and removing portions of the conformal silver layer on the dielectric layer, leaving a silver interconnect within the groove.
Abstract:
Silver interconnects (118) are formed by etching deep grooves (114) into an insulating layer (112) over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves (114) are etched with a truncated V- or U-shape, wider at the top than at any other vertical location, and have a minimum width of 0.25 µm or less. An optional adhesion layer and a barrier layer are sputtered onto surfaces of the groove, including the sidewalls, followed by sputter deposition of a seed layer. Where aluminum is employed as the seed layer, a zincating process may then be optionally employed to promote adhesion of silver to the seed layer. The groove (114) is then filled with silver (116) by plating in a silver solution, or with silver and copper by plating in a copper solution followed by plating in a silver solution. The filled groove (114) which results does not exhibit voids ordinarily resulting from sputter deposition of metal into such narrow, deep grooves, although seams may be intermittently present in portions of the filled groove where metal plated from the opposing sidewalls did not fuse flawlessly at the point of convergence. Portions of the silver (116) and other layers above the insulating material (112) are then removed by chemical-mechanical polishing, leaving a silver interconnect (118) connected to the exposed portion of the contact region (110) and extending over adjacent insulating regions to another contact region or a bond pad. Silver interconnects (118) thus formed may have smaller cross-sections, and thus a greater density in a given area, than conventional metallic interconnects.
Abstract:
A method of forming interconnects in an integrated circuit, comprising: forming a dielectric layer over a substrate; forming a groove (114) for an interconnect in the dielectric layer; forming an aluminium seed layer over the upper surface of the dielectric layer, over sidewalls of the groove, and over a bottom of the groove to a thickness of approximately 200 Å; zincating the substrate to form a zinc coating on the aluminium seed layer; plating the substrate with silver to form a conformal silver layer (116) on an upper surface of the dielectric layer and on sidewalls of the groove, filling an unfilled portion of the groove; and removing portions of the conformal silver layer on the dielectric layer, leaving a silver interconnect within the groove.