公开(公告)号：EP0973195B1

公开(公告)日：2012-04-11

申请号：EP99304867.7

申请日：1999-06-22

Applicant: STMicroelectronics, Inc.

Inventor： Chan, Tsiu C. ,  Chiu, Anthony M. ,  Smith, Gregory C.

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/532

CPC classification number: H01L21/76873 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1321931B1

公开(公告)日：2005-11-09

申请号：EP02258372.8

申请日：2002-12-04

Applicant: STMicroelectronics, Inc.

Inventor： Chiu, Anthony M. ,  Thomas, Danielle A.

IPC: G11B7/135 ,  G02B6/00 ,  G11B7/12

CPC classification number: G11B7/1372 ,  G02B6/4214 ,  G02B6/43 ,  G11B7/123

公开(公告)号：EP1333487A2

公开(公告)日：2003-08-06

申请号：EP03250551.3

申请日：2003-01-29

Applicant: STMicroelectronics, Inc.

Inventor： Siegel, Harry Michael ,  Chiu, Anthony M.

IPC: H01L23/14 ,  H01L21/60

CPC classification number: H01L21/52 ,  H01L23/544 ,  H01L24/48 ,  H01L24/83 ,  H01L2223/54473 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/854 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A system and method is disclosed for aligning an integrated circuit die on an integrated circuit substrate. A plurality of deposits of deformable material are placed on the substrate where the integrated circuit die is to be aligned. In one advantageous embodiment a stamping tool is indexed to a first tooling hole and to a second tooling hole in the substrate. The stamping tool imprints the deposits of deformable material to a tolerance of less than one hundred microns with respect to the first and second tooling holes. The imprinted portions of the deposits to form a pocket for receiving the integrated circuit die. This enables the integrated circuit die to be precisely aligned on the substrate in three dimensions.

Abstract translation: 一种系统和方法被游离缺失盘用于对准到集成电路上集合电路基板。 的可变形材料的沉积物的多个被放置在其中待对准这是集成电路衬底。 在一个有利实施例的冲压工具被索引到第一模具孔和在衬底的第二定位孔。 冲压工具烙印可变形材料的存款小于100微米的相对于第一和第二定位孔的公差。 沉积物的压印部分，以形成一个口袋，用于接收集成电路，其。 这使得集成电路是在三维空间中在基板上精确地对准。

公开(公告)号：EP1646102B1

公开(公告)日：2008-11-26

申请号：EP05256167.7

申请日：2005-10-03

Applicant: STMicroelectronics, Inc.

Inventor： Chiu, Anthony M.

IPC: H01M8/06

CPC classification number: H01M8/0612 ,  H01M8/04089 ,  H01M8/04201 ,  H01M8/04291 ,  H01M8/0656 ,  H01M8/186 ,  H01M2008/1095 ,  Y02E60/528

公开(公告)号：EP1548824A2

公开(公告)日：2005-06-29

申请号：EP04257575.3

申请日：2004-12-06

Applicant: STMicroelectronics, Inc.

Inventor： Chiu, Anthony M. ,  Tee, Tong Yan

IPC: H01L23/00

CPC classification number: H01L21/4821 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/32245 ,  H01L2924/00014 ,  H05K3/341 ,  H05K3/3442 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/10727 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2224/45099

Abstract: A system and method is disclosed for improving solder joint reliability in an integrated circuit package. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.

公开(公告)号：EP0742682B1

公开(公告)日：2005-02-23

申请号：EP96302902.0

申请日：1996-04-24

Applicant: STMicroelectronics, Inc.

Inventor： Hundt, Michael J. ,  Chiu, Anthony M.

IPC: H05K7/10

CPC classification number: H05K7/1069 ,  H01L23/4093 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

公开(公告)号：EP1351294A2

公开(公告)日：2003-10-08

申请号：EP03251346.7

申请日：2003-03-06

Applicant: STMicroelectronics, Inc.

Inventor： Thomas, Danielle A. ,  Siegel, Harry Michael ,  Do Bento Vieira, Antonio A. ,  Chiu, Anthony M.

IPC: H01L23/485 ,  H01L23/31 ,  H01L21/60

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  H01L2924/00014

Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.

Abstract translation: 的系统和方法是光盘为游离缺失在集成电路提供再分布金属层。 最终钝化加上之前再分布金属层是由在集成电路的负载金属层制造所述集成电路的过程中形成。 最后金属层提供用于在倒装芯片互连使用焊料凸点焊盘位点。 再分布金属层可以是（1）通过淀积在倒数第二个金属层，以开口在介电层的平坦层，或（2）沉积在连接到倒数第二个金属层的通孔的阵列。 焊料凸块焊盘之间的空间沉积有窄迹线下面连接有源电路区域。 最终钝化层被沉积，以确保产品的可靠性。

公开(公告)号：EP1548824B1

公开(公告)日：2013-02-27

申请号：EP04257575.3

申请日：2004-12-06

Applicant: STMicroelectronics, Inc.

Inventor： Chiu, Anthony M. ,  Tee, Tong Yan

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L21/4821 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/32245 ,  H01L2924/00014 ,  H05K3/341 ,  H05K3/3442 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/10727 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2224/45099

公开(公告)号：EP1018698B1

公开(公告)日：2009-04-22

申请号：EP99310543.6

申请日：1999-12-23

Applicant: STMicroelectronics, Inc.

Inventor： Chiu, Anthony M.

IPC: G06K9/00 ,  G06K9/20

CPC classification number: G06K9/00053

公开(公告)号：EP1732113A2

公开(公告)日：2006-12-13

申请号：EP06076564.1

申请日：1999-06-22

Applicant: STMicroelectronics, Inc.

Inventor： Chan, Tsiu C. ,  Chiu, Anthony M. ,  Smith, Gregory C.

IPC: H01L21/288 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76873 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming interconnects in an integrated circuit, comprising: forming a dielectric layer over a substrate; forming a groove for an interconnect in the dielectric layer; forming an aluminium seed layer over the upper surface of the dielectric layer, over sidewalls of the groove, and over a bottom of the groove to a thickness of approximately 200 Å; zincating the substrate to form a zinc coating on the aluminium seed layer; plating the substrate with silver to form a conformal silver layer on an upper surface of the dielectric layer and on sidewalls of the groove, filling an unfilled portion of the groove; and removing portions of the conformal silver layer on the dielectric layer, leaving a silver interconnect within the groove.

Abstract translation: 一种在集成电路中形成互连的方法，包括：在衬底上形成电介质层; 在所述电介质层中形成用于互连的凹槽（114）; 在所述电介质层的上表面上方，在所述凹槽的侧壁上方，并在所述凹槽的底部上方形成厚度约为的铝种子层; 对基材进行锌化以在铝籽晶层上形成锌涂层; 用银镀覆衬底以在电介质层的上表面和槽的侧壁上形成共形银层（116），填充凹槽的未填充部分; 并且去除介电层上的共形银层的部分，在槽内留下银互连。