公开(公告)号：EP1351294A2

公开(公告)日：2003-10-08

申请号：EP03251346.7

申请日：2003-03-06

Applicant: STMicroelectronics, Inc.

Inventor： Thomas, Danielle A. ,  Siegel, Harry Michael ,  Do Bento Vieira, Antonio A. ,  Chiu, Anthony M.

IPC: H01L23/485 ,  H01L23/31 ,  H01L21/60

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  H01L2924/00014

Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.

Abstract translation: 的系统和方法是光盘为游离缺失在集成电路提供再分布金属层。 最终钝化加上之前再分布金属层是由在集成电路的负载金属层制造所述集成电路的过程中形成。 最后金属层提供用于在倒装芯片互连使用焊料凸点焊盘位点。 再分布金属层可以是（1）通过淀积在倒数第二个金属层，以开口在介电层的平坦层，或（2）沉积在连接到倒数第二个金属层的通孔的阵列。 焊料凸块焊盘之间的空间沉积有窄迹线下面连接有源电路区域。 最终钝化层被沉积，以确保产品的可靠性。

公开(公告)号：EP1018699A3

公开(公告)日：2000-12-06

申请号：EP99310544.4

申请日：1999-12-23

Applicant: STMicroelectronics, Inc.

Inventor： Thomas, Danielle A. ,  Fang, Ming

IPC: G06K9/00

CPC classification number: G06K9/00053

Abstract: A structure and method for dissipating charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry a gap being formed conformally between adjacent plates and a topographic discharge grid over the underlying dielectric layer and wherein the topographic discharge grid fills at least a portion of the gap between the plates over the dielectric layer and diffuses electrostatic charges at the surface of the integrated circuit.

公开(公告)号：EP1017009A2

公开(公告)日：2000-07-05

申请号：EP99310531.1

申请日：1999-12-23

Applicant: STMicroelectronics, Inc.

Inventor： Lepert, Arnaud Yves ,  Thomas, Danielle A. ,  A Do-Bento-Vieira, Antonio

IPC: G06K9/00

CPC classification number: G06K9/00053

Abstract: A structure and method is disclosed for grounding an electrostatic discharge device of an integrated circuit to dissipate electrostatic charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry and a conductive layer disposed over the underlying dielectric layer, wherein the conductive layer diffuses electrostatic charges at the surface of the integrated circuit to ground. The conductive material not only dissipates electrostatic charges to the ground, but may also protect at least a portion of the edge of the sensor chip from mechanical stress.

Abstract translation: 公开了一种用于使集成电路的静电放电装置接地以消散静电电荷的结构和方法，该静电电荷包括设置在传感器电路的电容器板上的下面的介电层和设置在下面的介电层上的导电层，其中导电层扩散静电电荷 在集成电路的表面接地。 导电材料不仅将静电电荷耗散到地面，而且还可以保护传感器芯片的边缘的至少一部分免受机械应力。

公开(公告)号：EP1073117A3

公开(公告)日：2005-07-06

申请号：EP00305713.0

申请日：2000-07-06

Applicant: STMicroelectronics, Inc.

Inventor： Thomas, Danielle A.

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/642 ,  G06K9/00053 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide "scratch" protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material is employed for each metallization level between the surface and the active regions, including contacts and vias, landing pads, interconnects, capacitive electrodes, and electrostatic discharge protection lines.

公开(公告)号：EP1333500A3

公开(公告)日：2004-06-30

申请号：EP03250654.5

申请日：2003-01-31

Applicant: STMicroelectronics, Inc.

Inventor： Thomas, Danielle A. ,  Thomas, Gilles E.

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/1462 ,  H01L27/1463

Abstract: Fast and efficient photodiodes with different structures are fabricated using CMOS process technology by adapting transistor structures to form the diode structures. The anode regions of the photodiodes correspond to either PLDD regions of PMOS transistors or P-wells of NMOS transistors to provide two different photodiode structures with different anode region depths and thus different drift region thicknesses. An antireflective film used on the silicon surface of the photodiodes is employed as a silicide-blocking mask at other locations of the device.

公开(公告)号：EP1408442A2

公开(公告)日：2004-04-14

申请号：EP03256359.5

申请日：2003-10-09

Applicant: STMicroelectronics, Inc.

Inventor： Fang, Ming ,  Wang, Fuchao ,  Thomas, Danielle A.

IPC: G06K9/20 ,  H01L27/02

CPC classification number: G06K9/00053

Abstract: A fingerprint detector having a smooth sensing surface for contact with a fingerprint includes capacitive sensor plates defining an array of sensor cells below the sensing surface and tungsten ESD protection grid lines surrounding each sensor cell. The sensing surface is defined by an alumina layer with the tungsten grid lines embedded therein. The alumina layer provides a sensing surface with improved scratch resistance. The resulting detector is more sensitive in its capacitive sensing due to the relatively high dielectric constant of the alumina layer.

Abstract translation: 指纹检测器装置具有：（i）半导体衬底; （ii）形成在所述基板上的电容式传感器单元的阵列; （iii）具有围绕每个电池的栅格线（96）的钨格栅和外围地线（98）; 和（iv）设置在电池上方的氧化铝层。 栅格埋在氧化铝层中。 氧化铝层和网格具有暴露的表面部分，用于接触按压在检测器装置上的手指的指纹。 还包括用于制造指纹检测器的方法的独立权利要求，包括：（a）提供具有晶体管区域的半导体衬底（50）; （b）在衬底上形成导电层以互连晶体管; （c）在导电层之上形成平坦化的绝缘层; （d）在平坦化绝缘层上界定平面化绝缘层上的共面电容器板（76,78），其中通孔（82）穿过平坦化的绝缘层到下面的导电层的部分; （e）在电容器板之上和绝缘的上方沉积氧化铝层（108）; （f）在氧化铝层内限定开口; （f）在氧化铝层上和开口内沉积氮化钛膜; （g）在氮化钛层上沉积钨层; （h）选择性地蚀回钨层以去除除了开口内的钨; 和（i）在氧化铝层的表面上除去氮化钛。

公开(公告)号：EP1018697A3

公开(公告)日：2000-12-06

申请号：EP99310538.6

申请日：1999-12-23

Applicant: STMicroelectronics, Inc.

Inventor： Lepert, Arnaud Yves ,  Thomas, Danielle A. ,  Do-Bento-Vieira, Antonio

IPC: G06K9/00

CPC classification number: G06K9/00053

Abstract: A structure and method for creating a contact between a conductive layer and a pad for dissipating electrostatic charges comprising the steps of, forming a pad and a composite insulating layer between and over conductive plates on a substrate, wherein the insulating layer isolates and protects the conductive plates and pad from damage, the insulating layer comprising a dielectric region underlying a conductive layer. A passivation layer is formed over at least a portion of the conductive layer and a photoresist is patterned over at least a portion of the passivation. An opening is etched through the passivation and the insulating layers, wherein the photoresist and the conductive layer serve as masks. Finally, a conductive material is deposited in the opening to form an electrical contact between the pad and the conductive layer.

公开(公告)号：EP1018699A2

公开(公告)日：2000-07-12

申请号：EP99310544.4

申请日：1999-12-23

Applicant: STMicroelectronics, Inc.

Inventor： Thomas, Danielle A. ,  Fang, Ming

IPC: G06K9/00

CPC classification number: G06K9/00053

Abstract: A structure and method for dissipating charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry a gap being formed conformally between adjacent plates and a topographic discharge grid over the underlying dielectric layer and wherein the topographic discharge grid fills at least a portion of the gap between the plates over the dielectric layer and diffuses electrostatic charges at the surface of the integrated circuit.

Abstract translation: 一种用于耗散电荷的结构和方法，包括设置在传感器电路的电容器板之上的下面的介电层，相邻板之间保形地形成有间隙，并且在下面的介电层上方形成一个地形放电栅格，并且其中该地形放电栅格填充至少一部分 电介质层之间的间隙，并在集成电路的表面扩散静电电荷。

公开(公告)号：EP1018697A2

公开(公告)日：2000-07-12

申请号：EP99310538.6

申请日：1999-12-23

Applicant: STMicroelectronics, Inc.

Inventor： Lepert, Arnaud Yves ,  Thomas, Danielle A. ,  Do-Bento-Vieira, Antonio

IPC: G06K9/00

CPC classification number: G06K9/00053

Abstract: A structure and method for creating a contact between a conductive layer and a pad for dissipating electrostatic charges comprising the steps of, forming a pad and a composite insulating layer between and over conductive plates on a substrate, wherein the insulating layer isolates and protects the conductive plates and pad from damage, the insulating layer comprising a dielectric region underlying a conductive layer. A passivation layer is formed over at least a portion of the conductive layer and a photoresist is patterned over at least a portion of the passivation. An opening is etched through the passivation and the insulating layers, wherein the photoresist and the conductive layer serve as masks. Finally, a conductive material is deposited in the opening to form an electrical contact between the pad and the conductive layer.

Abstract translation: 一种用于在导电层和用于消散静电电荷的焊盘之间形成接触的结构和方法，包括以下步骤：在衬底上的导电板之间和之上形成焊盘和复合绝缘层，其中绝缘层隔离并保护导电层 板和焊盘免于损坏，绝缘层包括位于导电层下面的介电区域。 在导电层的至少一部分上方形成钝化层，并且在钝化层的至少一部分上图案化光致抗蚀剂。 蚀刻穿过钝化层和绝缘层的开口，其中光致抗蚀剂和导电层用作掩模。 最后，在开口中沉积导电材料以在焊盘和导电层之间形成电接触。

公开(公告)号：EP1411552A3

公开(公告)日：2008-07-02

申请号：EP03255931.2

申请日：2003-09-23

Applicant: STMicroelectronics, Inc.

Inventor： Thomas, Danielle A. ,  Deburre, Bruno J. ,  Thoma, Peter J.

IPC: G06K9/00

CPC classification number: G01L1/146 ,  G01L1/148 ,  G01N27/4145 ,  G01N27/4148 ,  G06K9/0002 ,  H01L27/307 ,  H01L51/0508

Abstract: Sensor cells are arranged in an array in an organic semiconductor layer. Row and column select circuitry addresses the cells of the array one cell at a time to determine the presence of an object, such as a fingerprint ridge or valley, contacting or proximate to a sensing surface above each cell. Control circuitry can be provided in a companion silicon chip or in a second layer of organic semiconductor material to communicate with the array and an associated system processor. The array of sensor cells can be fabricated using a flexible polymer substrate that is peeled off and disposed of after contacts have been patterned on the organic semiconductor layer. The organic semiconductor layer can be used with a superimposed reactive interface layer to detect specific chemical substances in a test medium.